參數(shù)資料
型號: PPC405EZ-CSAfffTx
廠商: Applied Micro Circuits Corp.
英文描述: PowerPC 405EZ Embedded Processor
中文描述: 嵌入式處理器的PowerPC 405EZ
文件頁數(shù): 43/54頁
文件大小: 362K
代理商: PPC405EZ-CSAFFFTX
PPC405EZ – PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
AMCC Proprietary
43
Preliminary Data Sheet
Table 9. Recommended DC Operating Conditions
Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended
conditions can affect device reliability.
Parameter
Symbol
Minimum
Typical
Maximum
Unit
Notes
Logic Supply Voltage
V
DD
+1.425
+1.5
+1.575
V
I/O Supply Voltage (for non-EBC I/O)
OV
DD
1
+3.0
+3.3
+3.6
V
I/O Supply Voltage (for EBC I/O)
OV
DD
2
+3.0
+3.3
+3.6
(see Note 1)
V
1
PLL Analog Supply Voltage
PLL_AV
DD
+1.4
+1.5
+1.6
V
ADC Analog Supply Voltage
ADC_AV
DD
+3.135
+3.3
+3.465
V
DAC Analog Supply Voltage
DAC_AV
DD
+3.135
+3.3
+3.465
V
I/O Input Low (3.3V LVTTL)
V
IL
0
+0.8
V
I/O Input High (3.3V LVTTL)
V
IH
+2.0
+3.6
V
I/O Output Low (3.3V LVTTL)
V
OL
0
+0.4
V
I/O Output High (3.3V LVTTL)
V
OH
+2.4
+3.6
V
I/O High (USB, 5V tolerant)
V
OH
+2.8
V
I/O Low (USB, 5V tolerant)
V
OL
+0.3
V
I/O Input High (IIC)
V
IH
0.7OV
DD
OV
DD
+ 0.3
V
I/O Input Low (IIC)
V
IL
0.3
+0.3OV
DD
V
I/O Output High (IIC)
V
IH
V
I/O Output Low (IIC)
V
OL
0
+0.4
V
Input Leakage Current
(no pull-up or pull-down)
I
IL1
0
0
μ
A
Input Leakage Current
(with internal pull-down)
I
IL2
0
200
μ
A
I/O Maximum Allowable Overshoot
(3.3V LVTTL)
V
MAO
+3.9
V
I/O Maximum Allowable Undershoot
(3.3V LVTTL)
V
MAU
0.6
V
Case Temperature
T
C
40
+105
°
C
Notes:
1. When using CRAM or PSRAM memory on the EBC interface, this voltage must be limited to a maximum of +3.3V. This is a limitation
imposed by the CRAM/PSRAM devices, not the PPC405EZ.
Table 10. Input Capacitance
Parameter
Symbol
Maximum
Unit
Notes
3.3V LVTTL I/O
C
IN1
1.9
pF
USB 5V Tolerant I/O
C
IN2
3.2
pF
IIC I/O
C
IN3
5.8
pF
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