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參數(shù)資料
| 型號： | PPC405EZ-CSAfffTx |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | PowerPC 405EZ Embedded Processor |
| 中文描述： | 嵌入式處理器的PowerPC 405EZ |
| 文件頁數(shù)： | 36/54頁 |
| 文件大?。?/td> | 362K |
| 代理商： | PPC405EZ-CSAFFFTX |
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PPC405EZ – PowerPC 405EZ Embedded Processor
36
AMCC Proprietary
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
System Interface
SysClk
System input clock.
I
3.3V LVTTL
SysErr
Machine check exception has occurred.
O
3.3V LVTTL
SysReset
Main system reset. This signal may be driven by the PPC405EZ to
cause a board level reset to occur.
I
3.3V LVTTL
TestEn
Test enable. Reserved for manufacturing LSSD test.
I
3.3V LVTTL
5
DebugEn
Debug enable.
I
3.3V LVTTL
5
Halt
External request to stop the processor.
I
3.3V LVTTL
4
TmrClk
Processor timer external input.
I
3.3V LVTTL
GPIO000:03
General purpose I/O. All of the GPIO signals are multiplexed with
other signals. Which signal a pin is connected to depends on the
setting of bits in the GPIO registers.
I/O
3.3V LVTTL
GPIO004:05
I/O
3.3V LVTTL
5
GPIO006:08
I/O
3.3V LVTTL
GPIO009
I/O
3.3V LVTTL
4
GPIO010:11
I/O
3.3V LVTTL
GPIO012:19
I/O
3.3V LVTTL
5
GPIO019:27
I/O
3.3V LVTTL
GPIO028:31
GPIO100:12
I/O
3.3V LVTTL
5
GPIO113:14
I/O
3.3V LVTTL
GPIO115:21
I/O
3.3V LVTTL
5
Trace Interface
TrcClk
Trace interface clock. Operates at half the CPU core frequency.
I
3.3V LVTTL
TS1E
TS2E
Even trace execution status.
I
3.3V LVTTL
TS1O
TS2O
Odd trace execution status.
I
3.3V LVTTL
TS3:6
Trace status.
I
3.3V LVTTL
Chameleon Timer Interface
PWM_DivClk
Divided-down clock.
O
3.3V LVTTL
PWM_OE0
PWM 0 Output enable input.
I
3.3V LVTTL
4
PWM_OE1:3
PWM 1:3 Output enable input.
I
3.3V LVTTL
PWM_TBA
Time Base A.
I/O
3.3V LVTTL
PWM_1:15
PWM Interface bus.
I/O
3.3V LVTTL
5
Table 6. Signal Functional Description (Sheet 2 of 6)
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 34 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 34 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
Signal Name
Description
I/O
Type
Notes
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PPC405GP-3BE133C | Power PC 405GP Embedded Processor |
| PPC405GP-3KE133C | Power PC 405GP Embedded Processor |
| PPC405GP-3KE133CZ | Power PC 405GP Embedded Processor |
| PPC405GP-3KE200C | Power PC 405GP Embedded Processor |
| PPC405GP-3KE200CZ | Power PC 405GP Embedded Processor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PPC405GP-3BE133C | 制造商:AppliedMicro 功能描述:MPU 405GP RISC 32BIT 0.25UM 133MHZ 3.3V 456PIN EBGA - Trays |
| PPC405GP-3BE133CZ | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:Power PC 405GP Embedded Processor |
| PPC405GP-3BE200C | 制造商:AppliedMicro 功能描述:MPU 405GP RISC 32-Bit 0.25um 200MHz 3.3V 456-Pin EBGA Tray |
| PPC405GP-3BE200CZ | 制造商:AppliedMicro 功能描述:MPU 405GP RISC 32-Bit 0.25um 200MHz 3.3V 456-Pin EBGA T/R |
| PPC405GP-3BE266C | 制造商:AppliedMicro 功能描述:MPU 405GP RISC 32-Bit 0.25um 266MHz 3.3V 456-Pin EBGA Tray |
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