參數(shù)資料
型號： PPC405EZ-CSAfffTx
廠商： Applied Micro Circuits Corp.
英文描述： PowerPC 405EZ Embedded Processor
中文描述： 嵌入式處理器的PowerPC 405EZ
文件頁數(shù)： 14/54頁
文件大小： 362K
代理商： PPC405EZ-CSAFFFTX
PPC405EZ – PowerPC 405EZ Embedded Processor
14
AMCC Proprietary
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Universal Interrupt Controller (UIC)
The Universal Interrupt Controller (UIC) provides the control, status, and communications necessary between the
various sources of interrupts and the PPC405 processor.
Features include:
32 interrupt sources supported (5 external)
Generate interrupt on level (high or low) or edge (rising or falling)
Programmable as synchronous (edge-capture or level-sensitive) or asynchronous (edge- or level-sensitive
triggering)
Each interrupt source/bit programmable as critical or non critical
32-bit DCR bus interface
Optional interrupt handler vector generation
– Programmable vector base address
– Programmable vector offset size
– Programmable interrupt priority ordering
Programmable polarity for all interrupt types
Interrupts of the same type do not need to be in contiguous bit positions
Status registers provide: current state of all interrupts, current state of enabled interrupts
10/100 Ethernet
The Ethernet support provides a single 10/100 Mbps interface.
Features include:
ANSI/IEEE Std. 802.3 and IEEE 802.3u supplement compliant
Half-duplex and full-duplex supported
MII interface to external PHY
512 byte receive FIFOs with programmable thresholds
FCS control for transmit/receive packets
Multiple packet handling in transmit and receive FIFOs
Unicast, multicast, broadcast, and promiscuous address filtering
Two 64-bit hash filters for unicast and multicast frames
Automatic retransmission of collided frames
Runt frame rejection
Programmable inter-frame gap
IEEE 802.3x compliant for frame-based flow control mechanism, including self-assembled control frame
transmitting)
Wake-on-LAN and Power-over-Internet supported
Programmable internal/external loopback capabilities
32-bit OPB slave (MAC) and PLB master (MAL) interfaces
Extensive error/status vector generation for each processed packet
VLAN tag ID supported (according to IEEE Draft 802.3ac/D1.0 standard)
Programmable automatic source address inclusion/replacement for transmit packets
Programmable automatic Pad/FCS stripping for receive packets
Programmable VLAN Tag inclusion/replacement for transmit packets
IEEE 1588 Precision Timing Protocol Controller
In a distributed control system containing multiple clocks, this feature defines messages used to exchange timing
information for precision network synchronization purposes. A second UIC in the PPC405EZ is dedicated to
generating snapshot triggers to the IEEE 1588 PTP controller from any interrupt source in the chip.
相關(guān)PDF資料
PDF描述
PPC405GP-3BE133C Power PC 405GP Embedded Processor
PPC405GP-3KE133C Power PC 405GP Embedded Processor
PPC405GP-3KE133CZ Power PC 405GP Embedded Processor
PPC405GP-3KE200C Power PC 405GP Embedded Processor
PPC405GP-3KE200CZ Power PC 405GP Embedded Processor
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PPC405GP-3BE133C 制造商:AppliedMicro 功能描述:MPU 405GP RISC 32BIT 0.25UM 133MHZ 3.3V 456PIN EBGA - Trays
PPC405GP-3BE133CZ 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:Power PC 405GP Embedded Processor
PPC405GP-3BE200C 制造商:AppliedMicro 功能描述:MPU 405GP RISC 32-Bit 0.25um 200MHz 3.3V 456-Pin EBGA Tray
PPC405GP-3BE200CZ 制造商:AppliedMicro 功能描述:MPU 405GP RISC 32-Bit 0.25um 200MHz 3.3V 456-Pin EBGA T/R
PPC405GP-3BE266C 制造商:AppliedMicro 功能描述:MPU 405GP RISC 32-Bit 0.25um 266MHz 3.3V 456-Pin EBGA Tray
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*