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參數(shù)資料
| 型號： | PPC405EZ-CSAfffTx |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | PowerPC 405EZ Embedded Processor |
| 中文描述： | 嵌入式處理器的PowerPC 405EZ |
| 文件頁數(shù)： | 11/54頁 |
| 文件大?。?/td> | 362K |
| 代理商： | PPC405EZ-CSAFFFTX |
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PPC405EZ – PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
AMCC Proprietary
11
Preliminary Data Sheet
Universal Serial Bus Specification
Controller Area Network (CAN)
The CAN controller module supports the concept of mailboxes. It contains 32 receive buffers, each one with its
own message filter, and 32 transmit buffers with a prioritized arbitration scheme. For optimal support of Higher
Level Protocols (HLP) such as DeviceNet or SDC, the message filter covers the first two data bytes.
Features include:
CAN 2.0B protocol compliant
ISO 11898-1 compliant
32 Transmit message holding registers, programmable priority arbitration
Message abort command supported
32 Receive buffers (each with own message filter)
– Message filtering: ID, IDE, Remote Transmission Request (RTR), data byte 1, and data byte 2
Message buffers can be linked together to build bigger message arrays
Automatic RTR response handler
Message Abort command supported
Maximum baud rate of 1Mbps with 8MHz system clock
Listen-only for debugging supported
Global masking supported
32-bit OPB slave interface
Internal loopback
UART
The Universal Asynchronous Receiver/Transmitter (UART) interface provides two ports. The UART performs
serial-to-parallel conversion on data received from a peripheral device or a modem, and parallel-to-serial
conversion on data received from the processor.
Features include:
Two ports (UART_0 and UART_1)
Software modem control functions (CTS, RTS, DSR, DTR, RI, DCD) on UART_0
Programmable auto flow (data flow controlled by RTS and CTS signals)
5-, 6-, 7-, or 8-bit characters
Programmable start, stop, parity bit insertion
64 byte FIFOs to buffer Tx and Rx data
LIN sub-bus specification compliant - line break generation/detection and false start bit detection
Programmable internal/external loopback capabilities
Low Power and Sleep mode
Register conformance (after reset) to configuration of the NS16450 register set
Hold and shift registers (eliminate need for precise synchronization between processor and serial data in
character mode)
Complete status reporting
Full prioritized interrupt system controls
Independently controlled transmit, receive, line status, and data set interrupts
Programmable baud generator (divides serial clock input and generates 16x clock)
Ability to add/delete standard asynchronous communication bits such as start, stop, and parity to/from serial
data
Even, odd, or no-parity bit generation and detection
1-, 1.5-, or 2-stop bit generation
Variable baud rate
Internal diagnostic capability
相關(guān)PDF資料 |
PDF描述 |
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| PPC405GP-3BE133C | Power PC 405GP Embedded Processor |
| PPC405GP-3KE133C | Power PC 405GP Embedded Processor |
| PPC405GP-3KE133CZ | Power PC 405GP Embedded Processor |
| PPC405GP-3KE200C | Power PC 405GP Embedded Processor |
| PPC405GP-3KE200CZ | Power PC 405GP Embedded Processor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PPC405GP-3BE133C | 制造商:AppliedMicro 功能描述:MPU 405GP RISC 32BIT 0.25UM 133MHZ 3.3V 456PIN EBGA - Trays |
| PPC405GP-3BE133CZ | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:Power PC 405GP Embedded Processor |
| PPC405GP-3BE200C | 制造商:AppliedMicro 功能描述:MPU 405GP RISC 32-Bit 0.25um 200MHz 3.3V 456-Pin EBGA Tray |
| PPC405GP-3BE200CZ | 制造商:AppliedMicro 功能描述:MPU 405GP RISC 32-Bit 0.25um 200MHz 3.3V 456-Pin EBGA T/R |
| PPC405GP-3BE266C | 制造商:AppliedMicro 功能描述:MPU 405GP RISC 32-Bit 0.25um 266MHz 3.3V 456-Pin EBGA Tray |
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