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參數(shù)資料
| 型號： | PPC405EZ-CSAfffTx |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | PowerPC 405EZ Embedded Processor |
| 中文描述： | 嵌入式處理器的PowerPC 405EZ |
| 文件頁數(shù)： | 38/54頁 |
| 文件大?。?/td> | 362K |
| 代理商： | PPC405EZ-CSAFFFTX |
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PPC405EZ – PowerPC 405EZ Embedded Processor
38
AMCC Proprietary
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
External Peripheral Interface
CRAM_AdV
Address valid signal for PSRAM/CRAM support.
O
3.3V LVTTL
CRAM_Clk
PerClk gated for PSRAM/CRAM support.
O
3.3V LVTTL
PerAddr04:31
Memory address bus 4:31.
O
3.3V LVTTL
BusReq
External PLB bus request.
O
3.3V LVTTL
PerClk
Clock output.
O
3.3V LVTTL
PerCS0:7
Chip selects 0:7.
O
3.3V LVTTL
PerData00:31
Memory data bus 0:31.
I/O
3.3V LVTTL
5
PerOE
Output enable.
O
3.3V LVTTL
PerReady
Wait for PSRAM/CRAM support.
I
3.3V LVTTL
PerRW
Read/Write.
O
3.3V LVTTL
PerWBE0:3
Write bus enable 0:3.
O
3.3V LVTTL
DMAAck
External DMA peripheral acknowledge.
O
3.3V LVTTL
DMAEOT/TC
External DMA peripheral end-of-transmission/terminal count.
I/O
3.3V LVTTL
5
DMAReq
External peripheral DMA request.
I
3.3V LVTTL
5
HoldReq
External request for bus access.
I
3.3V LVTTL
HoldAck
External request acknowledge.
O
3.3V LVTTL
HoldPri
External bus request priority.
I
3.3V LVTTL
NAND Flash Interface
NFALE
Address latch enable.
O
3.3V LVTTL
NFCE0:3
Cchip selects 0:3.
O
3.3V LVTTL
NFCLE
Command latch enable.
O
3.3V LVTTL
NFData0:7
Data bits 0:7
I/O
3.3V LVTTL
NFRB
Read/Busy. If low, indicates that Read/Erase command is in process.
If high, indicates that the command is complete.
I
3.3V LVTTL
NFRE
Read enable.
O
3.3V LVTTL
NFWE
Write enable.
O
3.3V LVTTL
Serial Peripheral Interface
SPI_ClkOut
Serial peripheral interface clock.
O
3.3V LVTTL
SPI_DI
Master and slave input.
I
3.3V LVTTL
5
SPI_DO
Master and slave output.
O
3.3V LVTTL
SPI_SS0:3
Slave Select 0:3.
O
3.3V LVTTL
SPI_SS_In
Slave Select Input for multi-master collision detection.
I
3.3V LVTTL
Table 6. Signal Functional Description (Sheet 4 of 6)
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 34 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 34 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
Signal Name
Description
I/O
Type
Notes
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| PPC405GP-3BE133C | Power PC 405GP Embedded Processor |
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相關代理商/技術參數(shù) |
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| PPC405GP-3BE133C | 制造商:AppliedMicro 功能描述:MPU 405GP RISC 32BIT 0.25UM 133MHZ 3.3V 456PIN EBGA - Trays |
| PPC405GP-3BE133CZ | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:Power PC 405GP Embedded Processor |
| PPC405GP-3BE200C | 制造商:AppliedMicro 功能描述:MPU 405GP RISC 32-Bit 0.25um 200MHz 3.3V 456-Pin EBGA Tray |
| PPC405GP-3BE200CZ | 制造商:AppliedMicro 功能描述:MPU 405GP RISC 32-Bit 0.25um 200MHz 3.3V 456-Pin EBGA T/R |
| PPC405GP-3BE266C | 制造商:AppliedMicro 功能描述:MPU 405GP RISC 32-Bit 0.25um 266MHz 3.3V 456-Pin EBGA Tray |
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