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參數(shù)資料
| 型號： | PPC405EZ-CSAfffTx |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | PowerPC 405EZ Embedded Processor |
| 中文描述： | 嵌入式處理器的PowerPC 405EZ |
| 文件頁數(shù)： | 35/54頁 |
| 文件大?。?/td> | 362K |
| 代理商： | PPC405EZ-CSAFFFTX |
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PPC405EZ – PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
AMCC Proprietary
35
Preliminary Data Sheet
Signal Functional Descriptions
The following table provides a description of the I/O signals on the PPC405EZ.
Table 6. Signal Functional Description (Sheet 1 of 6)
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 34 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 34 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
Signal Name
Description
I/O
Type
Notes
Ethernet Interface
EMCCOL
Collision signal from the PHY.
I
3.3V LVTTL
5
EMCCRS
Carrier sense signal from the PHY.
I
3.3V LVTTL
5
EMCMDC
Management data clock to the PHY.
O
3.3V LVTTL
EMCMDIO
Management data I/O between the Ethernet controller and the PHY.
I/O
3.3V LVTTL
EMCRxClk
Input receive clock from the PHY.
I
3.3V LVTTL
Rcvr
EMCRxDV
Receive data valid.
I
3.3V LVTTL
5
EMCRxEr
Receive error from the PHY.
I
3.3V LVTTL
Rcvr
EMCRxD0:3
Receive data from the PHY.
EMCRxD3 is the msb.
I
3.3V LVTTL
5
EMCTxClk
Input transmit clock from the PHY.
I
3.3V LVTTL
EMCTxD0:3
Transmit data to the PHY.
EMCTxD3 is the msb.
O
3.3V LVTTL
EMCTxEn
Transmit enable.
O
3.3V LVTTL
EMCTxEr
Transmit error to the PHY.
O
3.3V LVTTL
IEEE 1588 Network Synchronization Interface
IEEE_1588TS
Test signal.
O
3.3V LVTTL
IIC Peripheral Interface
IIC0SClk
IIC Serial Clock.
I/O
3.3V IIC
1, 5
IIC0SData
IIC Serial Data.
I/O
3.3V IIC
1, 5
Interrupts Interface
IRQ0:4
Interrupt requests.
I
3.3V LVTTL
1, 5
JTAG Interface
TCK
Test clock.
I
3.3V LVTTL
Rcvr w/pull-up
5
TDI
Test data in.
I
3.3V LVTTL
5
TDO
Test data out.
O
3.3V LVTTL
TMS
Test mode select.
I
3.3V LVTTL
5
TRST
Test reset. Must be low at power-on to initialize the JTAG controller
and for normal operation of the PPC405EZ.
I
3.3V LVTTL
Rcvr w/pull-up
5
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