參數(shù)資料
型號： PPC405EZ-CSAfffTx
廠商： Applied Micro Circuits Corp.
英文描述： PowerPC 405EZ Embedded Processor
中文描述： 嵌入式處理器的PowerPC 405EZ
文件頁數(shù)： 41/54頁
文件大?。?/td> 362K
代理商： PPC405EZ-CSAFFFTX
PPC405EZ – PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
AMCC Proprietary
41
Preliminary Data Sheet
Ratings and Specifications
Table 7. Absolute Maximum Ratings
The absolute maximum ratings below are stress ratings only.
Operation at or beyond these maximum ratings can cause
permanent damage to the device. None of the performance specification contained in this document are guaranteed when
operating at these maximum ratings.
Characteristic
Symbol
Value
Unit
Notes
Supply Voltage (Internal Logic)
V
DD
0 to +1.6
V
Non-EBC I/O Supply Voltage
OV
DD
1
0 to +3.6
V
EBC I/O Supply Voltage
OV
DD
2
0 to +3.6
V
3
PLL Analog Supply Voltage
PLL_AV
DD
0 to +1.6
V
ADC Analog Supply Voltage
ADC_AV
DD
0 to +3.465
V
DAC Analog Supply Voltage
DAC_AV
DD
0 to +3.465
V
Input Voltage (3.3V LVTTL receivers)
V
IN
0 to +3.6
V
Input Voltage (5.0V LVTTL receivers)
V
IN
0 to +5.5
V
Storage Temperature Range
T
STG
-55 to +150
°
C
Case temperature under bias
T
C
-40 to +120
°
C
Junction temperature
T
JMax
+125
°
C
1. All voltages are specified with respect to GND.
2. The analog voltages use for the system PLL, the ADC, and the DAC can be derived from V
DD
and OV
DD
1, but must be filtered
as shown below before entering the PPC405EZ. Use a separate filter for each voltage. The maximum value for ADC_PLL and
DAC_PLL must be limited to the values shown in this table.
3. OV
DD
2 must be limited to a maximum value of +3.3V if CRAM/PSRAM devices are attached to the EBC interface. This is a
limitation imposed by the CRAM/PSRAM devices, not the PPC405EZ.
V
DD
C1
PLL_AV
DD
L1
L1 – Murata BLM18AG121SN1D
C1 – 0.1
μ
F ceramic
PLL_AGND
GND
OV
DD
1
C1
ADC_PLL, DAC_PLL
L1
L1 – Murata BLM18AG121SN1D
C1 – 0.1
μ
F ceramic
ADC_GND, DAC_GND
GND
C2 – 0.01
μ
F ceramic
C2
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