參數(shù)資料
型號(hào): PPC405EZ-CSAfffTx
廠商: Applied Micro Circuits Corp.
英文描述: PowerPC 405EZ Embedded Processor
中文描述: 嵌入式處理器的PowerPC 405EZ
文件頁(yè)數(shù): 49/54頁(yè)
文件大?。?/td> 362K
代理商: PPC405EZ-CSAFFFTX
PPC405EZ – PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
AMCC Proprietary
49
Preliminary Data Sheet
ADC_InTrig
ADC_VRef
DAC_CRef
DAC_IOutP
DAC_IPTrig
DAC_IRRef
DAC_VRef
DAC_GRef
PWM_DivClk
PWM_OE[0]
PWM_OE[1:3]
PWM_TBA
PWM_1:15
IEEE_1588TS
Interrupts Interface
[IRQ0:4]
JTAG Interface
TCK
TDI
TDO
TMS
TRST
System Interface
GPIO000:31
GPIO100:20
Halt
SysErr
SysReset
TestEn
DebugEn
SysClk
na
na
na
na
na
na
na
na
na
na
na
na
19.1
na
na
na
19.1
19.1
19.1
19.1
19.1
19.1
na
na
na
na
8.7
na
na
na
8.7
8.7
8.7
8.7
8.7
8.7
na
na
na
na
na
na
5
5
5
5
5
19.1
8.7
na
22.5
na
22.5
na
na
0
na
0
na
na
na
25
na
na
na
na
0
na
na
na
na
19.1
na
na
na
na
8.7
na
na
TCK
TCK
TCK
TCK
na
na
22.5
na
na
na
na
na
na
na
0
na
na
na
na
na
na
na
na
15
na
na
na
na
na
na
na
25.5
na
na
na
na
19.1
19.1
na
19.1
19.1
na
na
na
8.7
8.7
na
8.7
8.7
na
na
na
TCK
TCK
async
async
Table 15. I/O Specifications—All CPU Speeds (Sheet 2 of 2)
Notes:
1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. Timing shown is with EMAC noise filter
selected.
2. For all interfaces, I/O H is specified at 2.4 V and I/O L is specified at 0.4 V.
3. Maximum skew between IIC output signals is 6ns.
4. Maximum skew between all SPI output signals is 3ns. All SPI inputs signals are latched with less than 4ns of skew between
channels.
5. Maximum skew between all PWM output signals is 3.75ns. All PWM input signals are latched with less than 2.5ns of skew
between channels.
Signal
Input (ns)
Output (ns)
Output Current (mA)
I/O H
(min)
Clock
Notes
Setup Time
(T
IS
min)
Hold Time
(T
IH
min)
Valid Delay
(T
OV
max)
Hold Time
(T
OH
min)
I/O L
(min)
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