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S/UNI-ATLAS-3200 Telecom Standard Product Data Sheet
Preliminary
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990553, Issue 4
402
The POS-PHY Receive Interface is controlled by the S/UNI-ATLAS-3200 PHY Layer device.
All signals must be updated and sampled using RPP_CLK. The RPP_DAT bus, RPP_PAR,
RPP_MOD, RPP_SOP, RPP_EOP and RPP_ERR signals are valid in cycles for which RPP_VAL
is high. Outputs will not be updated by the POS-PHY Receive PHY interface when it samples
RPP_ENB deasserted. In the example below, RPP_ENB is deasserted by the Link Layer in cycle
4. The S/UNI-ATLAS-3200 interface samples it in cycle 5, and does not update the interface in
cycle 6. When transferring data, RPP_VAL is asserted and remains high until the internal FIFO
of the PHY layer device is empty, or a complete burst is transferred. A burst always ends at an
EOP. The RPP_SX signal is valid in the cycle for which RPP_VAL is low and RPP_ENB was
low in the previous cycle.
Figure 31 RxPHY POS-PHY Packet Transfer
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0000
D0
D1
D2
D14
D15
D16
D17 0001
D1
.......
......
0
0
2
0
RPP_CLK
RPP_SX
RPP_SOP
RPP_EOP
RPP_ERR
RPP_ENB
RPP_DAT[31:0]
RPP_MOD[1:0]
RPP_PAR
RPP_VAL
Figure 31 is an example of a multi-port PHY device with at least two channels. The PHY informs
the Link Layer device of the port address of the selected FIFO by asserting RPP_SX with the port
address on the RPP_DAT bus. The Link Layer may pause the Receive Interface at any time by
deasserting the RPP_ENB signal. The end of the packet is indicated with the RPP_EOP signal,
along with any error condition on RPP_ERR. The Receive POS-PHY interface bursts data in 16
word bursts. A burst always ends at an EOP, and RSX is always asserted before the start of
another burst. The Receive PHY interface selects PHY 1 for the next burst, which starts at cycle
15.