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S/UNI-ATLAS-3200 Telecom Standard Product Data Sheet
Preliminary
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990553, Issue 4
397
14 Functional Timing
14.1
POS-PHY Level 3
14.1.1 Ingress Packet Interface
When the S/UNI-ATLAS-3200 is required to carry a mix of cells and packets, a POS-PHY Level
3 interface is used. In the ingress direction, the S/UNI-ATLAS-3200 provides an Rx PHY
interface on the system side, and an Rx Link interface on the PHY side. Selection of ingress vs.
egress mode and POS vs UL3 signalling must be performed at startup.
Figure 27 illustrates the operation of the interface. The figure is valid for both the RxLink and
RxPHY blocks (on input and output, respectively), with the ‘x’ in the signal names replaced with
‘L’ for the RxLink and ‘P’ for RxPHY.
The POS-PHY Receive Interface is controlled by the PHY Layer. It is presumed that the Link
Layer device can accept data at full line rate, so backpressure is limited to a single RxP_ENB
signal. At the beginning of a transfer, RxP_SX is asserted to indicate that the PHY address is on
RxP_DAT. In the subsequent cycle, RxP_SOP is asserted to mark the first word of the packet. At
any time, the PHY layer may pause the transfer by deasserting RxP_VAL. At the end of a packet,
RxP_MOD becomes valid to indicate how many of the final 4 bytes (between 1 and 4) are valid.
RxP_ERR may be asserted in this cycle to indicate that the packet is in error. PHY devices
generally assert RERR to indicate that HDLC abort flags rather than normal HDLC flags were
received at the end of a packet; S/UNI-ATLAS-3200 will assert RPP_RERR when transmitting
packets if RLP_RERR was asserted when the packet was received or, configurably, if an interface
error such as a parity error was detected.