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S/UNI-ATLAS-3200 Telecom Standard Product Data Sheet
Preliminary
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990553, Issue 4
350
Register 0x289: TxL PHY Indirect Data
Bit
Type
Function
Default
31:14
Unused
X
13
R/W
PORT_X_MAP[5]
0
12
R/W
PORT_X_MAP[4]
0
11
R/W
PORT_X_MAP[3]
0
10
R/W
PORT_X_MAP[2]
0
9
R/W
PORT_X_MAP[1]
0
8
R/W
PORT_X_MAP[0]
0
7
R/W
Unused
0
6
R/W
Unused
0
5
R/W
Unused
0
4
R/W
Unused
0
3
R/W
BURST_SIZE[3]
0
2
R/W
BURST_SIZE[2]
0
1
R/W
BURST_SIZE[1]
1
0
R/W
BURST_SIZE[0]
1
The TxL PHY Indirect Data register is an indirect access register along with the TxL PHY
Indirect Address.
BURST_SIZE[3:0]
The BURST_SIZE data register specifies the maximum number of 16-byte blocks allowed to
be transferred on a PHY in POS-PHY mode before the next PHY in the calendar is
automatically selected. A burst is automatically terminated at the end of a packet, or when
the FIFO becomes empty. The maximum number of blocks in a burst is BURST_SIZE + 1,
so that the minimum Burst Size is 1 block (16 bytes), and the maximum burst size is 16
blocks (256 bytes). For PHYs carrying ATM cells over POS-PHY, BURST_SIZE must be set
to the default 0x3. This register is used only in POS mode, and may be changed during
operation.
PORT X MAP
The PORT_X_MAP bits are used to translate PHY addresses. On powerup, each internal
FIFO PHYID will map to the identical PHY port. If translation is needed, then the location
for the external (UL3 or POS-PHY3 bus) PHY address must be programmed with the value
of the desired internal FIFO PHYID. The TxLink calendar always refers to the external
PHYID; the rest of the device will act on the internal FIFO PHYID. If the PHYID is written
to a value greater then 47, then data on that PHY is ignored.