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RELEASED
PM73122 AAL1GATOR-32
DATASHEET
PMC-1981419
ISSUE 7
32 LINK CES/DBCES AAL1 SAR PROCESSOR
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
31
Line Mode
Line Interface Table
RAM2 Interface Table
High Speed
High Speed
Yes (if using 2 lines)
10.4 Line Interface Signals(Direct Low Speed)(132)
Pin Name
Type
Pin
No.
Function
LINE_MODE[1]
LINE_MODE[0]
Input
B5
AC1
Determines the mode of operation for the
line interface:
00)Direct Low Speed Mode
01)SBI Mode
10) H-MVIP Mode
11) High Speed Mode
Note: In Direct Low Speed Mode, one
UDF-HS (51 Mbps) line can be
supported. In High Speed Mode, two
UDF-HS (51 Mbps) lines can be
supported. In SBI Mode, two UDF-HS
(DS3) lines can be supported.
TL_SYNC[15]
TL_SYNC[14]
TL_SYNC[13]
TL_SYNC[12]
TL_SYNC[11]
TL_SYNC[10]
TL_SYNC[9]
TL_SYNC[8]
TL_SYNC[7]
TL_SYNC[6]
TL_SYNC[5]
TL_SYNC[4]
TL_SYNC[3]
TL_SYNC[2]
TL_SYNC[1]
TL_SYNC[0]
I/O
K24
AC15
AC11
AF7
AA1
N3
A5
B10
A4
E4
G4
G1
L4
R3
V1
W3
Transmit Line Synchronization 15 to 0
are the transmit frame synchronization
indicators used in SDF-MF and SDF-FR
modes. Depending on the value of
MF_SYNC_MODE in the LI_CFG_REG
register for the line, these signals either
indicate a frame boundary or a multi-
frame boundary. Depending on the value
of GEN_SYNC in the LIN_STR_MODE
register for that line, the sync signal is
either received from the corresponding
framer device 0 to 15 or it is generated
internally The Default mode of this signal
is to be a frame sync input.
When the MVIP_EN bit is set in
LS_Ln_CFG_REG then TL_SYNC[0] is
the F0B pin; the common frame sync.
Maximum output current (IMAX) = 6 mA