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RELEASED
PM73122 AAL1GATOR-32
DATASHEET
PMC-1981419
ISSUE 7
32 LINK CES/DBCES AAL1 SAR PROCESSOR
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
382
The HS_LIN_REG in A1SP0 and A1SP2 control the High Speed functionality.
The CLK_SOURCE_TX and CLK_SOURCE_RX fields in the LIN_STR_MODE
memory register control the clock mode. In high speed mode only “000” (clock is
an input), or “001” (loop timing) modes are permitted.
NOTE: Because internal link 16 is mapped to external line 2, the
LIN_STR_MODE memory register for line 2 of A1SP0 and line 0 of A1SP2 must
both be initialized and set to the same value.
The An_SW_RESET bit in the An_CMD_REG memory register functions as a
queue reset signal in high speed mode. If the state of LOOPBACK_ENABLE in
TRANSMIT_CONFIG is desired to be changed, the high speed queue must be
reset using the An_SW_RESET bit.
Also when re-activating a highspeed queue, if it is required that the first
sequence number of the new connection has to be 0, then the queue must be
reset using the An_SW_RESET bit.
Otherwise, clearing and setting the TX_ACTIVE bit in QUEUE_CONFIG can be
used to deactivate and activate the queue.
14.2.4.5
SBI Mode
In SBI mode the following items need to be properly configured:
Link type for the upper and lower 16 links.
> Link type can be E1, T1, DS3 and is configured by setting
LINK_TYPH[1:0] or LINK_TYPHL[1:0] in the SBI Link Configuration
Register (SBI_LNK_CFG_REG) to the appropriate value. All
LINK_TYP default to T1 type.
The SPE type for each of the 3 SBI SPEs.
> SPE type can be E1, T1, or DS3 and is configured by setting
SPEn_TYP bit in the SBI Bus Configuration Register
(SBI_BUS_CFG_REG) to the appropriate value. All SPEs_TYP default
to T1 type.
> Each SPE must be enabled or disabled by writing appropriate value
into SPEn_ENBL bit in the SBI Bus Configuration Register. All SPEs
default to being enabled.
Receive Serial Link Clock Selection