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RELEASED
PM73122 AAL1GATOR-32
DATASHEET
PMC-1981419
ISSUE 7
32 LINK CES/DBCES AAL1 SAR PROCESSOR
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
304
Table 32 TRIB_TYP Encoding
CAS
Enabled
Framed
Transparent
VT
TRIB_TYP
Description
True
True
False
00
Structured with
CAS
False
True
False
01
Structured without
CAS
False
False
False
10
Unstructured
False
False
True
11
Transparent VT
(not supported)
Notes:
CAS can only be enabled for a Structured (framed) tributary.
“Framed” means framing information available – may be channelized or
unchannelized.
“Unframed” means no framing information available.
CLK_MSTR
The CLK_MSTR bit is used to specify whether the Extract block functions as
a clock master or a clock slave. When this bit is a ‘1’ the Extract block is a
clock master.
The CLK_MSTR configuration bits are OR’d with the CLK_MSTR bit in the
SBI_BUS_CFG_REG to allow the chip level to force master mode for all
tributaries. The default state of these bits will be clock slave.
CLK_MODE[1:0]
The CLK_MODE[1:0] field is used to choose the method of tributary clock
synthesis. After receiving tributary bytes from the SBI bus, PISO synthesizes
serial clocks for the A1SP TFTC’s using one of the following methods. The
Phase field method synthesizes a clock which most accurately reproduces
the original source clock. When implementing T1/E1 SRTS across the SBI
bus, the Phase method is required.