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RELEASED
PM73122 AAL1GATOR-32
DATASHEET
PMC-1981419
ISSUE 7
32 LINK CES/DBCES AAL1 SAR PROCESSOR
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
405
Figure 97 UI_SRC_INTF Start-of-Transfer Timing (Utopia 2 PHY Mode)
AAL1 Ad
AAL1_Ad
P1
P2
P3
P
D1
D2
D3
D
RPHY_CLK(i)
RPHY_ADDR(i)
RPHY_CLAV(o)
RPHY_ENB(i)
RPHY_SOC(o)
RPHY_PAR(o)
RPHY_DATA(o)
The end-of-transfer behavior is shown in Figure 98. As with Utopia 1 mode, the
state of RPHY_CLAV reflects the current cell transfer status and so remains
asserted until the last data byte/word. The SRC_INTF in this example does not
have another cell to send, so RPHY_CLAV shows a low value after the transfer.
Figure 98 UI_SRC_INTF End-of-Transfer Timing (Utopia 2 PHY Mode)
AAL1 Addr
D24
D25
D26
D27
D50
D51
D52
D53
RPHY_CLK(i)
RPHY_ADDR(i)
RPHY_CLAV(o)
RPHY_ENB(i)
RPHY_SOC(o)
RPHY_DATA(o) (16-bit)
RPHY_DATA(o) (8-bit)
Figure 99 is a functional timing of the SRC_INTF for the start of a cell transfer
when configured as an Any-PHY compliant receive slave. During a polling
operation, when the SRC_INTF determines that the UI_SRC_ADDR_CFG
address is on the bus it responds by driving RPHY_CLAV two cycles later. If
CS_MODE_EN is set in the UI_SRC_CFG register then CSB must also be
driven low one cycle after the RPHY_ADDR for proper response. If the
SRC_INTF has a cell to send it will drive RPHY_CLAV high and, as a result, the
master will activate RPHY_ENB to initiate a transfer. As with Utopia 2, the
SRC_INTF is selected if its address is on RPHY_ADDR inputs during the cycle
before RPHY_ENB goes low and in response transmits an entire cell.
RPHY_RSX is driven high during the prepended byte address and RPHY_SOC
is driven high during the first header byte of the ATM cell. Since data transfer
pausing is not supported, once a transfer is initiated, RPHY_ENB should remain