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RELEASED
PM73122 AAL1GATOR-32
DATASHEET
PMC-1981419
ISSUE 7
32 LINK CES/DBCES AAL1 SAR PROCESSOR
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
186
Table 17 AAL1gator-32 Memory Map
A[19:17]
Description
“000”
A1SP0 memory registers
“001”
A1SP1 memory registers
“010”
A1SP2 memory registers
“011”
A1SP3 memory registers
“10X”
Internal Normal Mode Registers
“11X”
Test Mode Registers
This section lists all the memory mapped registers and defines the bit fields of
each register. The memory mapping for one A1SP is shown. The memory
mapping for each A1SP is identical. The only difference is the value of A[18:17]
which is used to select each A1SP memory space.
A[18:17] = “00”
A1SP0
A[18:17] = “01”
A1SP1
A[18:17] = “10”
A1SP2
A[18:17] = “11”
A1SP3
12.1 Initialization
The memory must be initialized to 0 (unless otherwise indicated) before the
A1SP software reset is released, but the global software reset must be cleared
before writes to memory can take place. A number of data structures used by the
device in reserved areas depends on this initialization.
Notes:
All ports marked as “Reserved” must be initialized to 0 at initial setup.
Software modifications to these locations after setup will cause incorrect
operation.
All read/write port bits marked “Not used” must be written with the value 0 to
maintain software compatibility with future versions.
All read-only port bits marked “Not used” are driven with a 0 and should be
masked off by the software to maintain compatibility with future versions.