
PM5317 SPECTRA-9953 Telecom Standard Product Data Sheet
Release
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2000741, Issue 5
6
13.4
13.5
13.6
13.7
13.8
13.9
13.10
JTAG Test Access Port (TAP) Signals.......................................................................58
13.11
Digital Miscellaneous Signals....................................................................................59
13.12
Analog Miscellaneous Signals ..................................................................................60
13.13
Line Side Analog Power and Ground........................................................................60
13.14
System Side Analog Power and Ground...................................................................60
13.15
Power and Ground....................................................................................................62
14
Functional Description ..........................................................................................................86
14.1
Line LVDS Overview .................................................................................................86
14.2
LVDS Receivers and SIPO .......................................................................................87
14.3
SONET/SDH Receive Line Interface (SRLI).............................................................87
14.4
SONET/SDH Processing Slices................................................................................87
14.5
Receive Regenerator and Multiplexer Processor (RRMP) .......................................90
14.6
Receive Trail trace Processor (RTTP) ......................................................................94
14.7
Bit Error Monitor (SBER)...........................................................................................95
14.8
Receive High Order Path Processor (RHPP) ...........................................................95
14.9
SONET/SDH Alarm Reporting Controller (SARC) ..................................................103
14.10
SONET/SDH Transmit Line Interface (STLI) ..........................................................105
14.11
Transmit Regenerator Multiplexer Processor (TRMP)............................................105
14.12
Transmit Trail trace Processor (TTTP).....................................................................111
14.13
Transmit High Order Path Processor (THPP)..........................................................111
14.14
SONET/SDH High-order Pointer Interpreter (SHPI)............................................... 113
14.15
SONET/SDH Virtual Container Aligner (SVCA)...................................................... 113
14.16
System Side Interfaces ........................................................................................... 116
14.17
Space Slot Interchange (SSI).................................................................................. 118
14.18
8B/10B Encoder (T8TE).......................................................................................... 118
14.19
Receive 8B/10B TelecomBus Decoder (R8TD) ...................................................... 119
14.20
Add/Drop Clock Synthesis Unit...............................................................................121
14.21
Drop bus Transmit Serializer...................................................................................121
14.22
Drop bus LVDS Transmitter ....................................................................................121
Receive/Transmit Section/Line/Path Status and Alarms Signals..............................50
Receive Path BIP-8 Error Signals.............................................................................52
Transmit Section/Line Overhead Insertion Signals...................................................52
Drop/Add Serial TelecomBus Interface Signals ........................................................54
Transmit Path AIS Insertion Signals..........................................................................57
Microprocessor Interface Signals..............................................................................57