
PM5317 SPECTRA-9953 Telecom Standard Product Data Sheet
Release
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2000741, Issue 5
55
Pin Name
Type
Pin
No.
Function
timings.
AFP is sampled on the rising edge of SYSCLK.
DCMP
Input
M27
The
drop connection memory page
(DCMP) signal controls
the selection of the connection memory page in the Drop
space slot interchange. This input signal is XORED with an
internal DSSI register bit to select the Connection Memory
Page.
When (DCMP XOR DCMP_REG) is set high, connection
memory page 1 is selected. When low , connection memory
page 0 is selected. Refer to Functional Timing Section 15.4
for details of when the page change takes place.
DCMP is sampled on the rising edge of SYSCLK at the DFP
frame position.
ACMP
Input
F34
The
add connection memory page
(ACMP) signal controls
the selection of the connection memory page in the Add space
slot interchange. This input signal is XORED with an internal
ASSI register bit to select the Connection Memory Page.
When (ACMP XOR ACMP_reg) is set high, connection
memory page 1 is selected. When low, connection memory
page 0 is selected. Refer to Functional Timing Section 15.4 for
details of when the page change takes place.
ACMP is sampled on the rising edge of SYSCLK at the AFP
frame position.
DD4_p[3]
DD4_n[3]
DD4_p[2]
DD4_n[2]
DD4_p[1]
DD4_n[1]
DD4_p[0]
DD4_n[0]
DD3_p[3]
DD3_n[3]
DD3_p[2]
DD3_n[2]
DD3_p[1]
DD3_n[1]
DD3_p[0]
DD3_n[0]
DD2_p[3]
DD2_n[3]
DD2_p[2]
DD2_n[2]
DD2_p[1]
DD2_n[1]
DD2_p[0]
DD2_n[0]
DD1_p[3]
DD1_n[3]
Analog
LVDS
Output
AK34
AJ33
AH32
AG31
AF30
AE29
AJ34
AH33
AD34
AC33
AE34
AD33
AC28
AB27
AD32
AC31
AA32
Y31
AA30
Y29
Y34
W33
W34
V33
T34
U33
The
differential drop data
(DD[N]_p/n[3:0]) serial link carries
in bit serial format the single STS-192/STM-64 or quad
STS-48/STM-16 frame data received by the SPECTRA-9953.
Each differential pair carries a constituent STS-12/STM-4 of
the data stream. For quad STS-48/STM-16 mode, each DD[N]
group carries a full STS-48/STM-16 stream. For STS-
192/STM-64 mode, DD[1] carries STS-48 #1 (STM-16 #1)
while DD[4] carries STS-48 #4 (STM-16 #4).
Data on DD[N]_p/n[3:0] is encoded in an 8B/10B format
extended from IEEE Std. 802.3. The 8B/10B character bit ‘a(chǎn)’
is transmitted first and the bit ‘j’ is transmitted last.
The sixteen differential pairs in DD[N]_p/n[4:1] are frequency
locked but not phase locked. DD[N]_p/n[4:1] are nominally
777.6 Mbps data streams.