
PM5317 SPECTRA-9953 Telecom Standard Product Data Sheet
Release
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2000741, Issue 5
511
18
Functional Timing
18.1 Line Interface Functional Timing
The SPECTRA-9953 device complies with the OIF STS-192/STM-64 SERDES Interface
Revision 3.1. When the SPECTRA-9953 is used to process an STS-192/STM-64 SONET/SDH
stream, the RXDATA/TXDATA bus carries two bytes and is sampled/updated on the rising edge
of the RXCLK[2]/TXCLK[2]. When four STS-48/STM-16 are processed, each
RXDATA[N][3:0]/TXDATA[N][3:0] carries a nibble and is sampled/updated on the rising edge
of the RXCLK[N]/TXCLK[N]. Figure 35 shows as an example the functional timings of the
receive line side.
Figure 35 SPECTRA-9953 Line Interface Functional Timing
B1, B2
B3, B4
B5, B6
B7, B8
STS-192/STM-64 RDATA[15:0]
STS-192/STM-64 mode
B1[7:4]
B1[3:0]
B2[7:4]
B2[3:0]
STS-48/STM-16 #1 RDATA[1][3:0]
Quad STS-48/STM-16 mode
B1[7:4]
B1[3:0]
B2[7:4]
B2[3:0]
B1[7:4]
B1[3:0]
B2[7:4]
B2[3:0]
STS-48/STM-16 #2 RDATA[2][3:0]
STS-48/STM-16 #3 RDATA[3][3:0]
STS-48/STM-16 #4 RDATA[4][3:0]
RXCLK[2]_622MHz
B1[7:4]
B1[3:0]
B2[7:4]
B2[3:0]
RXCLK[1]_622MHz
RXCLK[2]_622MHz
RXCLK[3]_622MHz
RXCLK[4]_622MHz
Transmit line interface input and output framing pulses are considered asynchronous. An
internal low speed clock (77.76 MHz) is used to detect a rising edge on TXFPI[N] and to update
TXFPO[N]. TXFPI[N] rising edge is detected and used to force an outgoing framing pulse on
the corresponding Aligner (SVCA). TXFPO[N] is driven high for one internal 77.76 MHz clock
to indicate the approximate position of the first framing byte (A1). As shown in Figure 36,
TXFPO is asserted high for approximately eight TXCLK clock cycles when processing an STS-
192/STM-64 stream to indicate the first 16 bytes of the SONET/SDH frame (A1 bytes).