參數(shù)資料
型號(hào)： PI7C7300
廠商： Pericom Semiconductor Corp.
英文描述： 3-PORT PCI-to-PCI BRIDGE
中文描述： 3端口PCI至PCI橋
文件頁(yè)數(shù)： 59/109頁(yè)
文件大?。?/td> 779K
代理商： PI7C7300
PI7C7300A
3-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 59 OF 109
09/25/03 Revision 1.09
0
2
1
1
Delayed Write
Delayed Write
Delayed Write
Downstream
Upstream
Upstream
Secondary
Primary
Secondary
1 / 1
x / x
x / x
X
= don’t care
2
The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus.
Table 7-6 shows assertion of S_PERR# that is set under the following conditions:
!
PI7C7300A is either the target of a write transaction or the initiator of a read
transaction on the secondary bus.
!
The parity error response bit must be set in the bridge control register of secondary
interface.
!
PI7C7300A detects a data parity error on the secondary bus or detects P_PERR#
asserted during the completion phase of an upstream delayed write transaction on the
target (primary) bus.
Table 7-6 ASSERTION OF S_PERR#
S_PERR#
Transaction Type
Direction
Bus Where Error
Was Detected
Primary/
Secondary Parity
Error Response
Bits
x / x
x / 1
x / x
x / x
x / x
x / x
x / x
x / 1
x / x
x / x
1 / 1
x / 1
1 (de-asserted)
0 (asserted)
1
1
1
1
1
0
1
1
0
2
0
X
= don’t care
2
The parity error was detected on the target (secondary) bus but not on
the initiator (primary) bus.
Read
Read
Read
Read
Posted Write
Posted Write
Posted Write
Posted Write
Delayed Write
Delayed Write
Delayed Write
Delayed Write
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Table 7-7 shows assertion of P_SERR#. This signal is set under the following conditions:
!
PI7C7300A has detected P_PERR# asserted on an upstream posted write transaction
or S_PERR# asserted on a downstream posted write transaction.
!
PI7C7300A did not detect the parity error as a target of the posted write transaction.
!
The parity error response bit on the command register and the parity error response
bit on the bridge control register must both be set.
!
The SERR# enable bit must be set in the command register.
Table 7-7 ASSERTION OF P_SERR# FOR DATA PARITY ERRORS
P_SERR#
Transaction Type
Direction
Bus Where Error
Was Detected
Primary /
Secondary Parity
Error Response
Bits
相關(guān)PDF資料
PDF描述
PI7C7300A 3-PORT PCI-to-PCI BRIDGE
PI7C7300ANA 3-PORT PCI-to-PCI BRIDGE
PI7C8140A 2 PORT PCI TO PCI BRIDGE PLX PCI 6140 COMPARISON
PI7C8148B 2-PORT PCI-to-PCI BRIDGE PLX PC16152 COMPARISON
PI7C8150B-33 PCI Bridge | Asynchronous 2-Port PCI Bridge
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PI7C7300A 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:3-PORT PCI-to-PCI BRIDGE
PI7C7300AEVB-3 功能描述:界面開發(fā)工具 3 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評(píng)估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V
PI7C7300ANA 制造商:Pericom Semiconductor Corporation 功能描述:PCI-to-PCI Bridge 272-Pin BGA 制造商:Pericom Semiconductor Corporation 功能描述:PCI to PCI Bridge 272-Pin BGA
PI7C7300ANAE 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 3 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PI7C7300ANA-E 制造商:Pericom Semiconductor Corporation 功能描述:PCI-to-PCI Bridge 272-Pin BGA 制造商:Pericom Semiconductor Corporation 功能描述:PCI to PCI Bridge 272-Pin BGA
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