參數(shù)資料
型號: PI7C7300
廠商: Pericom Semiconductor Corp.
英文描述: 3-PORT PCI-to-PCI BRIDGE
中文描述: 3端口PCI至PCI橋
文件頁數(shù): 54/109頁
文件大?。?/td> 779K
代理商: PI7C7300
PI7C7300A
3-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 54 OF 109
09/25/03 Revision 1.09
For downstream delayed write transactions, when the parity error is detected on the
initiator bus and PI7C7300A has write status to return, the following events occur:
!
PI7C7300A first asserts P_TRDY# and then asserts P_PERR# two cycles later, if the
primary interface parity-error-response bit is set in the command register.
!
PI7C7300A sets the primary interface parity-error-detected bit in the status register.
!
Because there was not an exact data and parity match, the write status is not returned
and the transaction remains in the queue.
Similarly, for upstream delayed write transactions, when the parity error is detected on
the initiator bus and PI7C7300A has write status to return, the following events occur:
!
PI7C7300A first asserts S1_TRDY# or S2_TRDY# and then asserts S_PERR# two
cycles later, if the secondary interface parity-error-response bit is set in the bridge
control register (offset 3Ch).
!
PI7C7300A sets the secondary interface parity-error-detected bit in the secondary
status register.
!
Because there was not an exact data and parity match, the write status is not returned
and the transaction remains in the queue.
For downstream transactions, where the parity error is being passed back from the target
bus and the parity error condition was not originally detected on the initiator bus, the
following events occur:
!
PI7C7300A asserts P_PERR# two cycles after the data transfer, if the following are
both true:
-
The parity-error-response bit is set in the command register of the primary
interface.
-
The parity-error-response bit is set in the bridge control register of the
secondary interface.
!
For upstream transactions, when the parity error is being passed back from the target bus
and the parity error condition was not originally detected on the initiator bus, the
following events occur:
!
PI7C7300A asserts S_PERR# two cycles after the data transfer, if the following are
both true:
-
The parity error response bit is set in the command register of the primary
interface.
-
The parity error response bit is set in the bridge control register of the secondary
interface.
PI7C7300A completes the transaction normally.
!
PI7C7300A completes the transaction normally.
相關PDF資料
PDF描述
PI7C7300A 3-PORT PCI-to-PCI BRIDGE
PI7C7300ANA 3-PORT PCI-to-PCI BRIDGE
PI7C8140A 2 PORT PCI TO PCI BRIDGE PLX PCI 6140 COMPARISON
PI7C8148B 2-PORT PCI-to-PCI BRIDGE PLX PC16152 COMPARISON
PI7C8150B-33 PCI Bridge | Asynchronous 2-Port PCI Bridge
相關代理商/技術參數(shù)
參數(shù)描述
PI7C7300A 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:3-PORT PCI-to-PCI BRIDGE
PI7C7300AEVB-3 功能描述:界面開發(fā)工具 3 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V
PI7C7300ANA 制造商:Pericom Semiconductor Corporation 功能描述:PCI-to-PCI Bridge 272-Pin BGA 制造商:Pericom Semiconductor Corporation 功能描述:PCI to PCI Bridge 272-Pin BGA
PI7C7300ANAE 功能描述:外圍驅動器與原件 - PCI 3 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PI7C7300ANA-E 制造商:Pericom Semiconductor Corporation 功能描述:PCI-to-PCI Bridge 272-Pin BGA 制造商:Pericom Semiconductor Corporation 功能描述:PCI to PCI Bridge 272-Pin BGA