參數(shù)資料
型號(hào)： PI7C7300
廠商： Pericom Semiconductor Corp.
英文描述： 3-PORT PCI-to-PCI BRIDGE
中文描述： 3端口PCI至PCI橋
文件頁(yè)數(shù)： 35/109頁(yè)
文件大小： 779K
代理商： PI7C7300
PI7C7300A
3-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 35 OF 109
09/25/03 Revision 1.09
STOP#, DEVSEL# and TRDY# asserted. It signals that this is the last data transfer of the
transaction.
!
Target disconnect without data transfer
STOP# and DEVSEL# asserted with TRDY# de-asserted after previous data transfers
have been made. Indicates that no more data transfers will be made during this
transaction.
!
Target abort
STOP# asserted with DEVSEL# and TRDY# de-asserted. Indicates that target will never
be able to complete this transaction. DEVSEL# must be asserted for at least one cycle
during the transaction before the target abort is signaled.
4.9.1
MASTER TERMINATION INITIATED BY PI7C7300A
PI7C7300A, as an initiator, uses normal termination if DEVSEL# is returned by target
within five clock cycles of PI7C7300A’s assertion of FRAME# on the target bus. As an
initiator, PI7C7300A terminates a transaction when the following conditions are met:
!
During a delayed write transaction, a single DWORD is delivered.
!
During a non-prefetchable read transaction, a single DWORD is transferred from the
target.
!
During a prefetchable read transaction, a pre-fetch boundary is reached.
!
For a posted write transaction, all write data for the transaction is transferred from
data buffers to the target.
!
For burst transfer, with the exception of “Memory Write and Invalidate”
transactions, the master latency timer expires and the PI7C7300A’s bus grant is de-
asserted.
!
The target terminates the transaction with a retry, disconnect, or target abort.
If PI7C7300A is delivering posted write data when it terminates the transaction because
the master latency timer expires, it initiates another transaction to deliver the remaining
write data. The address of the transaction is updated to reflect the address of the current
DWORD to be delivered.
If PI7C7300A is pre-fetching read data when it terminates the transaction because the
master latency timer expires, it does not repeat the transaction to obtain more data.
4.9.2
MASTER ABORT RECEIVED BY PI7C7300A
If the initiator initiates a transaction on the target bus and does not detect DEVSEL#
returned by the target within five clock cycles of the assertion of FRAME#, PI7C7300A
terminates the transaction with a master abort. This sets the received-master-abort bit in
the status register corresponding to the target bus.
相關(guān)PDF資料
PDF描述
PI7C7300A 3-PORT PCI-to-PCI BRIDGE
PI7C7300ANA 3-PORT PCI-to-PCI BRIDGE
PI7C8140A 2 PORT PCI TO PCI BRIDGE PLX PCI 6140 COMPARISON
PI7C8148B 2-PORT PCI-to-PCI BRIDGE PLX PC16152 COMPARISON
PI7C8150B-33 PCI Bridge | Asynchronous 2-Port PCI Bridge
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PI7C7300A 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:3-PORT PCI-to-PCI BRIDGE
PI7C7300AEVB-3 功能描述:界面開(kāi)發(fā)工具 3 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評(píng)估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V
PI7C7300ANA 制造商:Pericom Semiconductor Corporation 功能描述:PCI-to-PCI Bridge 272-Pin BGA 制造商:Pericom Semiconductor Corporation 功能描述:PCI to PCI Bridge 272-Pin BGA
PI7C7300ANAE 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 3 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PI7C7300ANA-E 制造商:Pericom Semiconductor Corporation 功能描述:PCI-to-PCI Bridge 272-Pin BGA 制造商:Pericom Semiconductor Corporation 功能描述:PCI to PCI Bridge 272-Pin BGA
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