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參數(shù)資料
| 型號： | PI7C7300 |
| 廠商： | Pericom Semiconductor Corp. |
| 英文描述： | 3-PORT PCI-to-PCI BRIDGE |
| 中文描述： | 3端口PCI至PCI橋 |
| 文件頁數(shù)： | 107/109頁 |
| 文件大?。?/td> | 779K |
| 代理商： | PI7C7300 |
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PI7C7300A
3-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 107 OF 109
09/25/03 Revision 1.09
FREQUENTLY ASKED QUESTIONS
!
What is the function of SCAN_EN
SCAN_EN is for a full scan test or S_CLKIN select. During SCAN mode, SCAN_EN will be driven
to logic “0” or “l(fā)ogic “1” depending on functionality. During normal mode, if SCAN_EN is
connected to logic “0” (JP7 in the 1-2 position), S_CLKIN will be used for PLL test only when
PL_TM is active.
!
What is the function of SCAN_TM#
SCAN_TM# is for full scan test and power on reset for the PLL. SCAN_TM# should be connected to
logic “1” or to an RC path (R1 and C13) during normal operation.
!
How do you use the external arbiter
a) Disable the on chip arbiter by connecting S_CFN to logic “1” (JP4 in the 2-3 position).
b) Use S1_REQ#[0] as GRANT and S1_GNT#[0] as REQUEST on the S1 bus.
c) Use S2_REQ#[0] as GRANT and S2_GNT#[0] as REQUEST on the S2 bus.
!
What is the purpose of having JP1, JP2, and JP3
JP1, JP2, and JP3 are designed for easy access to the primary bus signals. You may connect any of
these pins to an oscilloscope or a logic analyzer for observation. No connection is required for normal
operation. The following table indicates which bus signals correspond to which pins.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
JP2
REQ
AD29
AD26
CBE3
AD21
AD21
CBE2
IRDY
LOCK
PAR
AD14
AD11
CBE0
AD6
AD5
AD0
JP3
JP1
AD31
GNT
AD28
AD30
AD25
AD27
AD23
AD24
AD20
AD22
AD20
AD22
FRAME
AD24
DVSEL
IRDY
PERR
STOP
CBE1
SERR
AD13
AD15
AD10
AD12
AD8
AD9
AD4
AD7
AD2
AD3
GND
AD1
!
What is the purpose for having U17, U19, and U20
U17, U19, and U20 are designed for easy access to the digital ground planes for observation.
!
How is the evaluation board constructed
The evaluation board is a six-layer PCB. The top and bottom layers (1 and 6) are for signals, power,
and ground routing. Layer 2 and layer 5 are ground planes. Layer 3 is a digital 3.3V power plane.
Layer 4 is a digital 5V power plane with an island of analog 3.3V power.
!
What is the function of S_CLKIN
The S_CLKIN pin is a test pin for the on chip PLL when PLL_TM is set to logic “1”.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PI7C7300A | 3-PORT PCI-to-PCI BRIDGE |
| PI7C7300ANA | 3-PORT PCI-to-PCI BRIDGE |
| PI7C8140A | 2 PORT PCI TO PCI BRIDGE PLX PCI 6140 COMPARISON |
| PI7C8148B | 2-PORT PCI-to-PCI BRIDGE PLX PC16152 COMPARISON |
| PI7C8150B-33 | PCI Bridge | Asynchronous 2-Port PCI Bridge |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C7300A | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:3-PORT PCI-to-PCI BRIDGE |
| PI7C7300AEVB-3 | 功能描述:界面開發(fā)工具 3 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| PI7C7300ANA | 制造商:Pericom Semiconductor Corporation 功能描述:PCI-to-PCI Bridge 272-Pin BGA 制造商:Pericom Semiconductor Corporation 功能描述:PCI to PCI Bridge 272-Pin BGA |
| PI7C7300ANAE | 功能描述:外圍驅(qū)動器與原件 - PCI 3 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C7300ANA-E | 制造商:Pericom Semiconductor Corporation 功能描述:PCI-to-PCI Bridge 272-Pin BGA 制造商:Pericom Semiconductor Corporation 功能描述:PCI to PCI Bridge 272-Pin BGA |
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