參數(shù)資料
型號(hào): PI7C7300
廠商: Pericom Semiconductor Corp.
英文描述: 3-PORT PCI-to-PCI BRIDGE
中文描述: 3端口PCI至PCI橋
文件頁(yè)數(shù): 37/109頁(yè)
文件大小: 779K
代理商: PI7C7300
PI7C7300A
3-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 37 OF 109
09/25/03 Revision 1.09
PI7C7300A makes 2
24
(default) or 2
32
(maximum) write attempts resulting in a response
of target retry.
Table 4-7 DELAYED WRITE TARGET TERMINATION RESPONSE
Target Termination
Normal
Response
Returning disconnect to initiator with first data transfer only if multiple data
phases requested.
Returning target retry to initiator. Continue write attempts to target
Returning disconnect to initiator with first data transfer only if multiple data
phases requested.
Returning target abort to initiator. Set received target abort bit in target interface
status register. Set signaled target abort bit in initiator interface status register.
Target Retry
Target Disconnect
Target Abort
After the PI7C7300A makes 2
24
(default) attempts of the same delayed write trans-action
on the target bus, PI7C7300A asserts P_SERR# if the SERR# enable bit (bit 8 of
command register for secondary bus S1 or S2) is set and the delayed-write-non- delivery
bit is not set. The delayed-write-non-delivery bit is bit 5 of P_SERR# event disable
register (offset 64h). PI7C7300A will report system error. See Section 7.4 for a
description of system error conditions.
POSTED WRITE TARGET TERMINATION RESPONSE
4.9.3.2
When PI7C7300A initiates a posted write transaction, the target termination cannot be
passed back to the initiator. Table 4-8 shows the response to each type of target
termination that occurs during a posted write transaction.
Table 4-8 RESPONSE TO POSTED WRITE TARGET TERMINATION
Target Termination
Normal
Target Retry
Target Disconnect
Target Abort
Repsonse
No additional action.
Repeating write transaction to target.
Initiate write transaction for delivering remaining posted write data.
Set received-target-abort bit in the target interface status register. Assert
P_SERR# if enabled, and set the signaled-system-error bit in primary status
register.
Note that when a target retry or target disconnect is returned and posted write data
associated with that transaction remains in the write buffers, PI7C7300A initiates another
write transaction to attempt to deliver the rest of the write data. If there is a target retry,
the exact same address will be driven as for the initial write trans-action attempt. If a
target disconnect is received, the address that is driven on a subsequent write transaction
attempt will be updated to reflect the address of the current DWORD. If the initial write
transaction is Memory-Write-and-Invalidate transaction, and a partial delivery of write
data to the target is performed before a target disconnect is received, PI7C7300A will use
the memory write command to deliver the rest of the write data. It is because an
incomplete cache line will be transferred in the subsequent write transaction attempt.
After the PI7C7300A makes 2
24
(default) write transaction attempts and fails to deliver
all posted write data associated with that transaction, PI7C7300A asserts P_SERR# if the
primary SERR# enable bit is set (bit 8 of command register for secondary bus S1 or S2)
and posted-write-non-delivery bit is not set. The posted-write-non-delivery bit is the bit 2
of P_SERR# event disable register (offset 64h). PI7C7300A will report system error. See
Section 7.4 for a discussion of system error conditions.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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PI7C7300ANA 制造商:Pericom Semiconductor Corporation 功能描述:PCI-to-PCI Bridge 272-Pin BGA 制造商:Pericom Semiconductor Corporation 功能描述:PCI to PCI Bridge 272-Pin BGA
PI7C7300ANAE 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 3 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PI7C7300ANA-E 制造商:Pericom Semiconductor Corporation 功能描述:PCI-to-PCI Bridge 272-Pin BGA 制造商:Pericom Semiconductor Corporation 功能描述:PCI to PCI Bridge 272-Pin BGA