![](http://datasheet.mmic.net.cn/260000/PI7C21P100_datasheet_15942603/PI7C21P100_66.png)
PI7C21P100
2-PORT PCI-X BRIDGE
ADVANCE INFORMATION
Page 66 of 77
June 10, 2005 Revision 1.06
9.4
BOUNDARY SCAN REGISTER
The boundary scan register is a required set of serial-shiftable register cells, formed by
connecting boundary scan cells placed at the device’s signal pins into a shift register path. The
VDD, VSS, and JTAG pins are NOT in the boundary-scan chain. The input to the shift
register is TDI and the output from the shift register is TDO. There are 4 different types of
boundary scan cells, based on the function of each signal pin.
The boundary scan register cells are dedicated logic and do not have any system function.
Data may be loaded into the boundary-scan register master cells from the device input pins
and output pin-drivers in parallel by the mandatory SAMPLE and EXTEST instructions.
Parallel loading takes place on the rising edge of TCK.
9.5
JTAG BOUNDARY REGISTER ORDER
Table 9-1 JTAG BOUNDARY SCAN REGISTER
Boundary Scan
Register Number
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Pin Name
P_ACK64#
P_AD[0]
P_AD[1]
P_AD[2]
P_AD[3]
P_AD[4]
P_AD[5]
P_AD[6]
P_AD[7]
P_AD[8]
P_AD[9]
P_AD[10]
P_AD[11]
P_AD[12]
P_AD[13]
P_AD[14]
P_AD[15]
P_AD[16]
P_AD[17]
P_AD[18]
P_AD[19]
P_AD[20]
P_AD[21]
P_AD[22]
P_AD[23]
P_AD[24]
P_AD[25]
P_AD[26]
P_AD[27]
P_AD[28]
P_AD[29]
P_AD[30]
P_AD[31]
Ball Location
A2
B13
C13
B14
C15
A19
B16
C16
A20
B17
C17
C19
D18
F22
F20
G22
B20
G21
H22
H21
J22
J21
K22
D23
K21
E23
K20
G23
L22
L21
M22
M21
J23
Type
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
Tri-state Control Cell
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240