![](http://datasheet.mmic.net.cn/260000/PI7C21P100_datasheet_15942603/PI7C21P100_64.png)
PI7C21P100
2-PORT PCI-X BRIDGE
ADVANCE INFORMATION
Page 64 of 77
June 10, 2005 Revision 1.06
BIT
20
FUNCTION
Private Device Mask 4
TYPE
RW
DESCRIPTION
Private Device Mask 4
0:
Rerouting disabled for device 4
1:
Block assertion of S_AD[20] for configuration transactions to
device 4 and assert S_AD[31] instead.
Reserved.
Returns 00 when read.
Private Device Mask 1
0:
Rerouting disabled for device 1
1:
Block assertion of S_AD[17] for configuration transactions to
device 1 and assert S_AD[31] instead.
Reserved.
Returns 000000000000000000 when read.
19:18
17
RESERVED
Private Device Mask 1
RW
RW
16:0
RESERVED
RW
8.1.64
MISCELLANEOUS CONTROL REGISTER 2 – OFFSET B8h
BIT
FUNCTION
TYPE
15
Short Term Caching
RW
DESCRIPTION
Short Term Caching
0:
Short term caching is disabled
1:
Short term caching is enabled.
Reserved.
Returns 00000 when read.
Primary Prefetching Persistence Control
0:
PI7C21P100 discontinue prefetching on the secondary bus when
the target disconnects, regardless of how much data has been
buffered
1:
PI7C21P100 continues prefetching on the secondary bus despite
target disconnects until either the byte count specified by Primary
Data Buffering Control Register has been prefetched, or the initiator
disconnects.
Secondary Prefetching Persistence Control
0:
PI7C21P100 discontinue prefetching on the primary bus when the
target disconnects, regardless of how much data has been buffered
1:
PI7C21P100 continues prefetching on the primary bus despite
target disconnects until either the byte count specified by Primary
Data Buffering Control Register has been prefetched, or the initiator
disconnects.
Reserved.
Returns 00h when read.
14:10
9
RESERVED
Primary Prefetching
Persistence Control
RO
RW
8
Secondary Prefetching
Persistence Control
RW
7:0
RESERVED
RO