參數(shù)資料
型號(hào)： PI7C21P100NH
廠商： Pericom Semiconductor Corp.
英文描述： 2-PORT PCI-X BRIDGE
中文描述： 2端口PCI - X橋接
文件頁(yè)數(shù)： 17/77頁(yè)
文件大?。?/td> 603K
代理商： PI7C21P100NH
PI7C21P100
2-PORT PCI-X BRIDGE
ADVANCE INFORMATION
Page 17 of 77
June 10, 2005 Revision 1.06
64BIT_DEV#
Y22
I
PCI-X Device Bus Width:
64BIT_DEV# sets bit 16 of
the PCI-X Bridge Status Register to support system
management software. This signal does not change the
behavior of the bridge.
0: Sets bit 16 of the PCI-X bridge status register to 1
1: Sets bit 16 of the PCI-X bridge status register to 0
Base Address Register Enable:
BAR_EN is used to
enable the base address at reset or power up. When
enabled, the 64-bit register at offset 10h and offset 14h is
used to claim a 1MB memory region.
0: Disabled – register returns 0 and no memory region is
claimed
1: Enabled – bits 63:20 can be written by software to
claim a 1MB memory region
IDSEL Reroute Enable:
Controls the IDSEL reroute
function at reset or power up. The reset value of the
secondary bus private device mask register is changed
according to the value of this pin.
0: Reset value of the secondary bus private device mask
register is 00000000h
1: Reset value of the secondary bus private device mask
register is 22F20000h
Opaque Region Enable:
Used to enable the opaque
memory region at reset or power up. Controls bit[0]
offset 70h.
0: Disable opaque memory address range
1: Enable opaque memory address range
Primary Configuration Busy:
Determines the value of
bit [2] offset 44h to sequence initialization on the
primary and secondary buses for applications that
require bridge configuration from the secondary bus.
Applications that do not require configuration from the
secondary bus should pull this pin down to ground.
0: Type 0 configuration commands accepted normally on
the primary bus.
1: Type 0 configuration commands are retried on the
primary bus.
Reserved.
Must be tied to ground.
BAR_EN
G2
I
IDSEL_ROUTE
AC22
I
OPAQUE_EN
AA18
I
P_CFG_BUSY
C6
I
RESERVED
D1
-
3.2.7
JTAG BOUNDARY SCAN AND TEST SIGNALS
Name
TCK
Pin #
F21
Type
IU
Description
Test Clock.
Used to clock state information and data
into and out of the PI721P100 during boundary scan.
Test Mode Select.
Used to control the state of the Test
Access Port controller.
Test Data Output.
Used as the serial output for the test
instructions and data from the test logic.
Test Data Input.
Serial input for the JTAG instructions
and test data.
Test Reset.
Active LOW signal to reset the Test Access
Port (TAP) controller into an initialized state.
TMS
D22
IU
TDO
B23
O
TDI
C22
IU
TRST#
C23
IU
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