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參數(shù)資料
| 型號： | PI7C21P100NH |
| 廠商： | Pericom Semiconductor Corp. |
| 英文描述： | 2-PORT PCI-X BRIDGE |
| 中文描述： | 2端口PCI - X橋接 |
| 文件頁數(shù)： | 58/77頁 |
| 文件大?。?/td> | 603K |
| 代理商： | PI7C21P100NH |
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PI7C21P100
2-PORT PCI-X BRIDGE
ADVANCE INFORMATION
Page 58 of 77
June 10, 2005 Revision 1.06
8.1.48
OPAQUE MEMORY BASE REGISTER – OFFSET 74h
BIT
FUNCTION
TYPE
15:4
Opaque Memory Base
Address
DESCRIPTION
Opaque Memory Base Address
Address bits[31:20] of the opaque memory base address in
conjunction with the opaque memory base upper 32-bit register and
opaque memory limit address. In this range, memory transactions are
not accepted by PI7C21P100 on both primary and secondary
interfaces.
Reset to 000h
Address Select
Returns 0001 when read to indicate 64-bit addressing.
RW
3:0
Address Select
RO
8.1.49
OPAQUE MEMORY LIMIT REGISTER – OFFSET 74h
BIT
FUNCTION
TYPE
31:20
Opaque Memory Limit
Address
DESCRIPTION
Opaque Memory Limit Address
Address bits[31:20] of the opaque memory limit address in
conjunction with the opaque memory limit upper 32-bit register and
opaque memory base address. In this range, memory transactions are
not accepted by PI7C21P100 on both primary and secondary
interfaces.
Reset to FFFh
Address Select
Returns 0001 when read to indicate 64-bit addressing.
RW
19:16
Address Select
RO
8.1.50
OPAQUE MEMORY BASE UPPER 32-BIT REGISTER – OFFSET 78h
BIT
FUNCTION
TYPE
DESCRIPTION
31:0
Opaque Memory Base
Upper 32-bit Register
Address bits[63:32] of the opaque memory base address. In this
range, memory transactions are not accepted by PI7C21P100 on both
primary and secondary interfaces.
Reset to FFFF FFFFh
RW
Opaque Memory Base Upper 32-bit Register
8.1.51
OPAQUE MEMORY LIMIT UPPER 32-BIT REGISTER – OFFSET
7Ch
BIT
FUNCTION
TYPE
DESCRIPTION
31:0
Opaque Memory Base
Upper 32-bit Register
Address bits[63:32] of the opaque memory limit address. In this
range, memory transactions are not accepted by PI7C21P100 on both
primary and secondary interfaces.
Reset to FFFF FFFFh
RW
Opaque Memory Base Upper 32-bit Register
8.1.52
PCI-X CAPABILITY ID REGISTER – OFFSET 80h
BIT
FUNCTION
TYPE
7:0
PCI-X Capability ID
RO
DESCRIPTION
PCI-X Capability ID
Returns 07h when read to indicate that this register set of the
Capabilities List is a PCI-X register set.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PI7C7100BNA | PCI Bus Interface/Controller |
| PI7C7100 | 3-Port PCI Bridge |
| PI7C7100CNA | 3-Port PCI Bridge |
| PI7C7300 | 3-PORT PCI-to-PCI BRIDGE |
| PI7C7300A | 3-PORT PCI-to-PCI BRIDGE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C21P100NHE | 功能描述:外圍驅(qū)動器與原件 - PCI 3 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C4025TRF4 | 制造商:Pericom Semiconductor Corporation 功能描述: |
| PI7C7100 | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:3-Port PCI Bridge |
| PI7C7100BNA | 制造商:Pericom Semiconductor Corporation 功能描述:3 PORT PCI TO PCI |
| PI7C7100CNA | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:3-Port PCI Bridge |
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