參數(shù)資料
型號(hào)： PI7C21P100NH
廠商： Pericom Semiconductor Corp.
英文描述： 2-PORT PCI-X BRIDGE
中文描述： 2端口PCI - X橋接
文件頁(yè)數(shù)： 53/77頁(yè)
文件大?。?/td> 603K
代理商： PI7C21P100NH
PI7C21P100
2-PORT PCI-X BRIDGE
ADVANCE INFORMATION
Page 53 of 77
June 10, 2005 Revision 1.06
BIT
2
FUNCTION
Downstream Memory
Read Prefetching
Dynamic Control
TYPE
RW
DESCRIPTION
Downstream Memory Read Prefetching Dynamic Control
0:
Enable downstream memory read prefetching dynamic control
1:
Disable downstream memory read prefetching dynamic control
Reset to 0
(Described in section 4.3.6)
Reserved.
Returns 00 when read.
1:0
RESERVED
RO
8.1.38
EXTENDED CHIP CONTROL REGISTER 2 – OFFSET 48h
BIT
FUNCTION
TYPE
11:10
Minimum Free Space in
Memory Data FIFO
Control (Secondary)
DESCRIPTION
Minimum Free Space in Memory Data FIFO Control
(Secondary)
Selects the minimum free space in the memory data FIFO to accept
memory writes on the secondary bus in PCI-X mode
00:
128 bytes of free space to accept memory writes
01:
256 bytes of free space to accept memory writes
10:
512 bytes of free space to accept memory writes
11:
128 bytes of free space to accept memory writes
Reset to 00
Minimum Free Space in Memory Data FIFO Control (Primary)
Selects the minimum free space in the memory data FIFO to accept
memory writes on the primary bus in PCI-X mode
00:
128 bytes of free space to accept memory writes
01:
256 bytes of free space to accept memory writes
10:
512 bytes of free space to accept memory writes
11:
128 bytes of free space to accept memory writes
Reset to 00
RW
9:8
Minimum Free Space in
Memory Data FIFO
Control (Primary)
RW
8.1.39
ARBITER MODE REGISTER – OFFSET 50h
BIT
FUNCTION
15:8
Arbiter Fairness
Counter
TYPE
RW
DESCRIPTION
Arbiter Fairness Counter
These bits are the initialization value of a counter used by the internal
arbiter. It controls the number of PCI bus cycles that the arbiter holds
a device’s PCI bus grant active after detecting a PCI bus request from
another device. The counter is reloaded whenever a new PCI bus
grant is asserted. For every new PCI bus grant, the counter is armed
to decrement when it detects the de-assertion of FRAME#. If the
arbiter fairness counter is set to 00h, the arbiter will not remove a
device’s PCI bus grant until the device has de-asserted its PCI bus
request.
Reset to 08h
GNT# Output Toggling Enable
0:
GNT# not de-asserted after granted master asserts FRAME#
1:
GNT# de-asserts for 1 clock after 2 clocks from the granted master
asserting FRAME#.
Reset to 0
Broken Master Refresh
0:
A broken master will be ignored forever except when it de-asserts
its REQ# for at least 1 clock
1:
Refresh broken master state after all other masters have been
served once.
Reset to 0
Reserved.
Returns 0000 when read.
Broken Master Timeout Enable
0:
Broken master timeout disabled
1:
Broken master timeout enabled. This enables the internal arbiter to
count 16 PCI bus cycles while waiting for FRAME# to become
active when a device’s PCI bus GNT# is active and the PCI bus is
idle. If the broken master timeout expires, the PCI bus GNT# for the
device is de-asserted.
Reset to 0
7
GNT# Output Toggling
Enable
RW
6
Broken Master Refresh
RW
5:2
1
RESERVED
Broken Master Timeout
Enable
RO
RW
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