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參數(shù)資料
| 型號(hào)： | PI7C21P100NH |
| 廠商： | Pericom Semiconductor Corp. |
| 英文描述： | 2-PORT PCI-X BRIDGE |
| 中文描述： | 2端口PCI - X橋接 |
| 文件頁數(shù)： | 46/77頁 |
| 文件大?。?/td> | 603K |
| 代理商： | PI7C21P100NH |
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PI7C21P100
2-PORT PCI-X BRIDGE
ADVANCE INFORMATION
Page 46 of 77
June 10, 2005 Revision 1.06
8.1.18
I/O BASE ADDRESS REGISTER – OFFSET 1Ch
BIT
FUNCTION
7:4
I/O Base Address
TYPE
RW
DESCRIPTION
Specifies the base of the I/O address range bits [15:12] and is used
with the I/O limit register and I/O base upper 16 bits and I/O limit
upper 16-bit registers
Reserved. Returns 00b when read.
Returns 01b when read to indicate PI7C21P100 supports 32-bit I/O
addressing
3:2
1:0
Reserved
32-bit I/O Addressing
RO
RO
8.1.19
I/O LIMIT REGISTER – OFFSET 1Ch
BIT
FUNCTION
15:12
I/O Limit Address
TYPE
RW
DESCRIPTION
Address bits[15:12] of the limit address for the address range of I/O
operations that are passed from primary to secondary
Reserved. Returns 00b when read.
Returns 01b when read to indicate PI7C21P100 supports 32-bit I/O
addressing
11:10
9:8
Reserved
32-bit I/O Addressing
RO
RO
8.1.20
SECONDARY STATUS REGISTER – OFFSET 1Ch
BIT
FUNCTION
TYPE
31
Detected Parity Error
RWC
DESCRIPTION
Detected Parity Error Status
0:
Address or data parity error not detected by PI7C21P100 on the
secondary
1:
Address or data parity error detected by PI7C21P100 on the
secondary
Reset to 0
Signaled System Error Status
0:
PI7C21P100 did not assert SERR# on the secondary
1:
PI7C21P100 asserted SERR# on the secondary
Reset to 0
Received Master Abort Status
0:
Transaction not terminated with a bus master abort on the
secondary
1:
Transaction terminated with a bus master abort on the secondary
Reset to 0
Received Target Abort Status
0:
Transaction not terminated with a target abort
1:
Transaction terminated with a target abort
Reset to 0
Signaled Target Abort Status
0:
Target device did not terminate transaction with a target abort
1:
Target device terminated transaction with a target abort
Reset to 0
DEVESEL# Timing Status
01:
Medium decoding.
Returns 01h when read.
Data Parity Error Status
0:
No data parity error detected on the secondary
1:
Data parity error detected on the secondary
Reset to 0
Fast Back-to-Back Status
0:
Target not capable of decoding fast back-to-back transactions in
PCI-X mode
1:
Target capable of decoding fast back-to-back transactions in
conventional PCI mode
Returns 0 in PCI-X mode and 1 in conventional PCI mode
Reserved.
Returns 0 when read.
30
Signaled System Error
RWC
29
Received Master Abort
RWC
28
Received Target Abort
RWC
27
Signaled Target Abort
RWC
26:25
DEVSEL# Timing
RO
24
Data Parity Error
RWC
23
Fast Back-to-Back
Enable
RO
22
Reserved
RO
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PI7C7100BNA | PCI Bus Interface/Controller |
| PI7C7100 | 3-Port PCI Bridge |
| PI7C7100CNA | 3-Port PCI Bridge |
| PI7C7300 | 3-PORT PCI-to-PCI BRIDGE |
| PI7C7300A | 3-PORT PCI-to-PCI BRIDGE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C21P100NHE | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 3 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C4025TRF4 | 制造商:Pericom Semiconductor Corporation 功能描述: |
| PI7C7100 | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:3-Port PCI Bridge |
| PI7C7100BNA | 制造商:Pericom Semiconductor Corporation 功能描述:3 PORT PCI TO PCI |
| PI7C7100CNA | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:3-Port PCI Bridge |
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