參數(shù)資料
型號(hào)： PI7C21P100NH
廠商： Pericom Semiconductor Corp.
英文描述： 2-PORT PCI-X BRIDGE
中文描述： 2端口PCI - X橋接
文件頁(yè)數(shù)： 51/77頁(yè)
文件大小： 603K
代理商： PI7C21P100NH
PI7C21P100
2-PORT PCI-X BRIDGE
ADVANCE INFORMATION
Page 51 of 77
June 10, 2005 Revision 1.06
8.1.35
SECONDARY DATA BUFFERING CONTROL REGISTER – OFFSET
40h
BIT
FUNCTION
TYPE
DESCRIPTION
31
RESERVED
RO
Reserved
. Returns 0h when read.
30.28
Maximum Memory
Read Byte Count
000:
512 bytes (default)
001:
128 bytes
010:
256 bytes
011:
512 bytes
100:
1024 bytes
101:
2048 bytes
110:
4096 bytes
111:
512 bytes
Maximum byte count is used by PI7C21P100 when generating read
requests on the primary interface in response to a memory read
operation initiated on the secondary interface which is in
conventional PCI mode and bits[9:8], bits[7:6], or bits[5:4] are set to
full prefetch.
Reset to 000
27
Enable Relaxed
Ordering
0:
Relaxed ordering is disabled in conventional PCI mode.
1:
At the secondary interface, read completions that occur after the
first read completion are allowed to bypass posted writes and
complete with a higher priority in conventional PCI mode.
In PCI-X mode, the relaxed ordering bit in the attribute field will
take precedence. Reset to 0
26
Secondary Special
Delayed Read Mode
Enable
command code changes.
1:
Allows any secondary master to change memory command code
(MR, MRL, MRM) after it has received a retry. PI7C21P100 will
complete the memory read transaction and return data back to the
primary bus master if the address and byte enables are the same.
This bit is ignored in PCI-X mode. Reset to 0
25:24
Secondary Read
Prefetch Mode
00:
One cache line prefetch if memory read address is in the
prefetchable range at the secondary interface
01:
Reserved
10:
Full prefetch if memory read address is in the prefetchable range
at the secondary interface.
11:
Disconnect on the first DWORD.
These bits are ignored in PCI-X mode. Reset to 00
23:22
Secondary Read Line
Prefetch Mode
00:
One cache line prefetch if memory read line address is in
prefetchable range at the secondary interface
01:
Reserved
10:
Full prefetch if memory read multiple address is in prefetchable
range at the secondary interface
11:
Reserved.
These bits are ignored if the secondary interface is in PCI-X mode.
21:20
Secondary Read
Multiple Prefetch Mode
00:
One cache line prefetch if memory read multiple address is in
prefetchable range at the secondary interface.
01:
Reserved.
10:
Full prefetch if memory read multiple address is in prefetchable
range at the secondary interface.
11:
Reserved.
These bits are ignored if the secondary interface is in PCI-X mode.
Reset to 10.
19:16
RESERVED
RO
Reserved.
Returns 0000 when read.
RW
Maximum Memory Read Byte Count
RW
Relaxed Ordering Enable
RW
Secondary Special Delayed Read Mode Enable
0:
Retry any secondary master which repeats its transaction with
RW
Secondary Read Prefetch Mode
RW
Secondary Read Line Prefetch Mode
RW
Secondary Read Multiple Prefetch Mode
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PI7C7100BNA 制造商:Pericom Semiconductor Corporation 功能描述:3 PORT PCI TO PCI
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