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參數(shù)資料
| 型號： | PF38F3050L0YUQ3A |
| 廠商： | INTEL CORP |
| 元件分類： | 存儲器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PBGA88 |
| 封裝： | 8 X 10 MM, 1.20 MM HEIGHT, ROHS COMPLIANT, SCSP-88 |
| 文件頁數(shù)： | 62/70頁 |
| 文件大小： | 1193K |
| 代理商： | PF38F3050L0YUQ3A |
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Intel StrataFlash Wireless Memory (L18 SCSP)
August 2006
Datasheet
Order Number: 314476-001
65
768-Mbit LQ Family with Synchronous PSRAM
Note: WAIT is configured as Active Low and asserted during delay.
12.5.2
PSRAM Burst Interrupt
In burst interrupt an on-going burst is ended and new burst command issued while
keeping CE# low (subject to tCSL restrictions.) To insure proper device operation, a
burst interrupt is prohibited until the previous burst-init command completes its first
valid data transaction. If a burst read is interrupted by a new burst command, the DQ
are put into a high-Z state (within tWHZ time period.) If a burst write is interrupted by
a new burst command, the write data is automatically masked regardless of UB#/LB#
setting. Also note, that prior to initiating a burst interrupt by taking ADV# low, the
ADV# high hold time of tHD must be met with respect to the previous clock cycle
Figure 35. Example of PSRAM Burst Suspend with Read Burst with Latency Code 2
D0
D1
D2
D3
tOD
tKOH
tAOE
tOL
tOD
tKOH
tACLK
tABA
tAOE
tOL
tWZ
tWK
tCWT
tCSL
tCSS
CLK
A[MAX:0]
ADV#
CE#
OE#
WE#
UB#/LB#
WAIT
DQ[15:0]
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