參數(shù)資料
型號(hào)： PF38F3050L0YUQ3A
廠商： INTEL CORP
元件分類： 存儲(chǔ)器
英文描述： SPECIALTY MEMORY CIRCUIT, PBGA88
封裝： 8 X 10 MM, 1.20 MM HEIGHT, ROHS COMPLIANT, SCSP-88
文件頁(yè)數(shù)： 44/70頁(yè)
文件大小： 1193K
代理商： PF38F3050L0YUQ3A
Intel StrataFlash Wireless Memory (L18 SCSP)
August 2006
Datasheet
Order Number: 314476-001
49
768-Mbit LQ Family with Synchronous PSRAM
Burst start address is latched on the rising edge of the clock;
To continue the synchronous read operation:
CE#, OE#, and both UB# and LB# must be asserted; and
ADV# must be deasserted;
The first data word is output after the number of clock cycles defined by the
programmed latency mode and latency count in the BCR. Subsequent data words are
output at successive clock cycles after the first data word.
WAIT output will be driven and should be monitored in Variable Latency mode.
WAIT may be ignored in fixed latency mode.
Both UB# and LB# must be held static low for the entire read access. The size of
the burst is also specified in the BCR.
Warning:
When operating the PSRAM as an ADMux I/O interface by connecting the lower sixteen
(16) addresses, A[15:0], to the data pins, ADV# must be de-asserted during any data
phase cycle.
11.1.4
PSRAM Asynchronous Fetch Control Register Read
In the Asynchronous (SRAM-type) mode the contents of the BCR and RCR can be read
asynchronously. To initiate an asynchronous Fetch Control Register (FCR):
CE#, OE#, CRE, and both UB# and LB# must be asserted;
WE# must be deasserted;
ADV# can be toggled to latch the address or held low for the entire read operation;
CLK must be held in a static low state.
Except for A19 and A18, all other address and data bits are don’t care. A19 and A18
specify the target register (RCR = 00b, BCR = 10b) The contents of the selected
register are available on the data bus after the specified access time has elapsed. WAIT
output will be driven but should be ignored for asynchronous operations.
Warning:
When operating the PSRAM as an ADMux I/O interface by connecting the lower sixteen
(16) addresses, A[15:0], to the data pins, ADV# must be de-asserted during any data
phase cycle.
11.2
PSRAM Writes
The PSRAM bus interface supports asynchronous single-word and synchronous burst-
mode writes. BCR15 defines whether asynchronous or synchronous mode is enabled.
11.2.1
PSRAM Asynchronous Write
In the Asynchronous (SRAM-type) mode and NOR-Flash mode, PSRAM write commands
are asynchronous. To initiate an asynchronous write operation:
CE# and WE# must be asserted;
UB# and LB# must be asserted appropriately depending on the data byte(s) that
are being written. UB# enables DQ[15:8] and LB# enables DQ[7:0].
CRE must be deasserted;
ADV# can be toggled to latch the address or held low for the entire read operation;
CLK must be held in a static state.
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