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參數(shù)資料
| 型號： | PF38F3050L0YUQ3A |
| 廠商： | INTEL CORP |
| 元件分類： | 存儲器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PBGA88 |
| 封裝： | 8 X 10 MM, 1.20 MM HEIGHT, ROHS COMPLIANT, SCSP-88 |
| 文件頁數(shù)： | 50/70頁 |
| 文件大?。?/td> | 1193K |
| 代理商： | PF38F3050L0YUQ3A |
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768-Mbit LQ Family with Synchronous PSRAM
Intel StrataFlash Wireless Memory (L18 SCSP)
Datasheet
August 2006
54
Order Number: 314476-001
768-Mbit LQ Family with Synchronous PSRAM
12.0
PSRAM Device Operation
12.1
PSRAM Operating Modes
The PSRAM can be used in three different modes:
SRAM (full asynchronous) mode: In this mode the PSRAM applies the standard
asynchronous SRAM protocol to perform read and write accesses. In additions,
reads may be performed in page mode if the page mode is properly enabled by
programming the RCR. In this mode the clock must always remain static low.
Fully Synchronous mode: In this mode, both read and write accesses are
performed synchronously with respect to the clock. Synchronous operations are
defined by the states of the control signals CE#, ADV#, OE#, WE# and UB#, LB#
at the positive (default) edge of the clock.
NOR-Flash mode: In this mode, reads are performed synchronously with respect to
the clock and writes are performed asynchronously. The asynchronous write
operation requires that the clock remain static low during the entire write.
Synchronous read operations are defined by the states of the control signals CE#,
ADV#, OE#, WE# and UB#, LB# at the positive (default) edge of the clock.
12.2
PSRAM Control Registers
The two control registers define the PSRAM device operation. The Bus Control Register
(BCR) defines how the PSRAM interacts with the system memory busy, and the Refresh
Control Register (RCR) defines low-power refresh modes. Both these registers are
loaded with default values on power-up and can be updated at any time using hardware
or software access method.
12.2.1
PSRAM Bus Control Register
The Bus Control Register (BCR) specifies the interface configurations. The Bus Control
Register is programmed via the Set Control Register command (with CRE = 1 and
A[19:18] = 10b) and retains the stored information until it is reprogrammed or the
device loses power.
Reserved bit fields of the BCR should be ignored during a Fetch Control Register
command as they may have undefined values even when set to 0b with a Set Control
Register command. The BCR contents can only be set or changed when the PSRAM is in
idle state.
Table 18. PSRAM Bus Control Register Map
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R
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DQ
[15:0]
DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
A
[MAX:0]
A22-
A20 A19 A18
A17-
A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
BCR Bit 22-
20 19 18
17-
16
15
14
13
12
11
10
9
8
7654
3
2
1
0
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