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參數(shù)資料
| 型號： | PF38F3050L0YUQ3A |
| 廠商： | INTEL CORP |
| 元件分類： | 存儲器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PBGA88 |
| 封裝： | 8 X 10 MM, 1.20 MM HEIGHT, ROHS COMPLIANT, SCSP-88 |
| 文件頁數(shù)： | 49/70頁 |
| 文件大?。?/td> | 1193K |
| 代理商： | PF38F3050L0YUQ3A |
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Intel StrataFlash Wireless Memory (L18 SCSP)
August 2006
Datasheet
Order Number: 314476-001
53
768-Mbit LQ Family with Synchronous PSRAM
During variable latency burst write operations and fixed latency burst write and read
operations the initial latency is fixed so the system is not required to monitor the WAIT
signal although the WAIT signal is fully functional and may be monitored by the
system. The system should terminate or interrupt the burst access to avoid row
boundary crossings in both fixed and variable latency mode.
To match with the Flash interfaces of different microprocessor types the polarity and
the timing of the WAIT signal can be configured. The polarity can be programmed to be
either active low or active high. The timing of the WAIT signal can be adjusted as well.
Depending on the BCR setting the WAIT signal will be either asserted at the same time
the data becomes invalid or it will be set active one clock period in advance.
In asynchronous mode including page mode, the WAIT signal is not used but stays
asserted as BCR10 is specified. In this case, the system should ignore the WAIT signal.
When the PSRAM is deselected or in deep power down, the WAIT output will be in a
high impedance state.
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| PF38F3050M0Y0CE0 | 制造商:Micron Technology Inc 功能描述:WIRELESS - Trays |
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