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參數(shù)資料
| 型號： | PF38F3050L0YUQ3A |
| 廠商： | INTEL CORP |
| 元件分類： | 存儲器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PBGA88 |
| 封裝： | 8 X 10 MM, 1.20 MM HEIGHT, ROHS COMPLIANT, SCSP-88 |
| 文件頁數(shù)： | 59/70頁 |
| 文件大?。?/td> | 1193K |
| 代理商： | PF38F3050L0YUQ3A |
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768-Mbit LQ Family with Synchronous PSRAM
Intel StrataFlash Wireless Memory (L18 SCSP)
Datasheet
August 2006
62
Order Number: 314476-001
768-Mbit LQ Family with Synchronous PSRAM
After applying the SCR command in asynchronous mode, CE# must be pulled high for
minimum of tCPH prior to initiating any subsequent command. After applying the SCR
command in synchronous mode, CE# must be pulled high for minimum of tCPBH prior
to initiating a subsequent synchronous command. Additionally, when applying the
synchronous SCR command CE# must remain low to complete a burst of one write
even though the DQ values are ignored by the PSRAM. To insure predictable device
behavior, an SCR command should not be terminated or interrupted prematurely and
ADV# should not go low more than one time prior to CE# being pulled high.
12.3.2
PSRAM Software Register Access
Software access of the registers uses a sequence of asynchronous read and
asynchronous write operations. First, two asynchronous reads to the maximum address
are performed followed by an asynchronous write to the maximum address. The data
values during this asynchronous write select the appropriate register.
During the fourth operation, DQ[15:0] transfer data in to or out of the bits [15:0] of
the registers.
During the software access sequence, it is necessary to:
Toggle CE# between every read or write command (so the Device can distinguish 4
separate cycles).
Maintain the address input until it is latched by ADV# or until CE# goes high. After
setting the control registers using the software access method, CE# must be pulled
high for minimum of tCPH prior to initiating any subsequent command.
To insure predictable device behavior, the fourth access cycle of the software access
should not be terminated or interrupted prematurely and ADV# should not go low
more than one time during each access where CE# is low
Furthermore, during the 3rd cycle of the software access, the asynchronous write
operation should be CE# controlled, that is on the 3rd cycle CE# must go high prior to
WE# and UB#/LB#.
Figure 33. PSRAM Loading Configurations Registers Using Software Access
MAX
XXXXh
Input
RCR: 0000h
BCR: 0001h
A[MAX:0]
CE#
OE#
WE#
UB#/LB#
DQ[15:0]
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| PF38F3050M0Y0CE0 | 制造商:Micron Technology Inc 功能描述:WIRELESS - Trays |
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| PF38F3050M0Y0CEB | 制造商:Micron Technology Inc 功能描述:8MX16/4MX16 MCP PLASTIC PBF TFBGA 1.8V COMBO - Tape and Reel |
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