參數(shù)資料
型號： PF38F3050L0YUQ3A
廠商： INTEL CORP
元件分類： 存儲器
英文描述： SPECIALTY MEMORY CIRCUIT, PBGA88
封裝： 8 X 10 MM, 1.20 MM HEIGHT, ROHS COMPLIANT, SCSP-88
文件頁數(shù)： 46/70頁
文件大?。?/td> 1193K
代理商： PF38F3050L0YUQ3A
768-Mbit LQ Family with Synchronous PSRAM
Intel StrataFlash Wireless Memory (L18 SCSP)
Datasheet
August 2006
50
Order Number: 314476-001
768-Mbit LQ Family with Synchronous PSRAM
The data to be written will be latched on the rising edge of CE#, WE# or UB#/LB#
whichever occurs first. WAIT output will be driven but should be ignored for
asynchronous-mode operations.
Warning:
When operating the PSRAM as an ADMux I/O interface by connecting the lower sixteen
(16) addresses, A[15:0], to the data pins, ADV# must be de-asserted during any data
phase cycle.
11.2.2
PSRAM Synchronous Write
In the Full Synchronous mode, PSRAM write operations are synchronous. A BURST INIT
WRITE command is used to initiate a synchronous write operation and latch the burst
start address. To initiate a synchronous write operation:
CE#, ADV#, and WE# must be asserted;
OE# and CRE must be deasserted; and
Burst start address is latched on the rising edge of the clock;
To continue the synchronous write operation:
CE#, and UB#/LB# must be asserted; and
ADV# must be deasserted;
The first data word is input after the number of clock cycles defined by the
programmed latency mode and latency count in the BCR. Subsequent data words are
input at successive clock cycles after the first data word. The size of the burst is also
specified in the BCR. WAIT output will be driven and may be monitored. But since
synchronous write is always at fixed latency regardless of the Latency Mode setting,
WAIT may be ignored. UB# or LB# may be deasserted to mask the associated data
byte.
Warning:
When operating the PSRAM as an ADMux I/O interface by connecting the lower sixteen
(16) addresses, A[15:0], to the data pins, ADV# must be de-asserted during any data
phase cycle.
11.2.3
PSRAM Asynchronous Set Control Register Write
In the Asynchronous (SRAM-type) mode and NOR-Flash mode the contents of the BCR
and RCR can be set asynchronously. To initiate an asynchronous Set Control Register:
CE#, WE#, and CRE must be asserted;
OE# must be deasserted;
ADV# can be toggled to latch the address or held low for the entire read operation;
CLK must be held in a static low state.
The DQ signals are ignored by the PSRAM. Address bits A19 and A18 specify the target
register (RCR = 00b, BCR = 10b.) The values of the remaining address bits are loaded
into the selected register. The Set Control Register command should only be issued
when the PSRAM is in the idle state (deselected).
Warning:
When operating the PSRAM as an ADMux I/O interface by connecting the lower sixteen
(16) addresses, A[15:0], to the data pins, ADV# must be de-asserted during any data
phase cycle.
相關(guān)PDF資料
PDF描述
PFC04108.2UHKT 1 ELEMENT, 8.2 uH, GENERAL PURPOSE INDUCTOR
PFC04101.8UHKT 1 ELEMENT, 1.8 uH, GENERAL PURPOSE INDUCTOR
PFC041022UHKB 1 ELEMENT, 22 uH, GENERAL PURPOSE INDUCTOR
PFC04102700UHKT 1 ELEMENT, 2700 uH, GENERAL PURPOSE INDUCTOR
PFC0410270UHKB 1 ELEMENT, 270 uH, GENERAL PURPOSE INDUCTOR
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PF38F3050M0Y0CE0 制造商:Micron Technology Inc 功能描述:WIRELESS - Trays
PF38F3050M0Y0CE3 制造商:Micron Technology Inc 功能描述:WIRELESS - Trays
PF38F3050M0Y0CEA 制造商:Micron Technology Inc 功能描述:128BA/64PS SCSP 1.8 X16C HF - Trays 制造商:Micron Technology Inc 功能描述:IC FLASH 192M
PF38F3050M0Y0CEB 制造商:Micron Technology Inc 功能描述:8MX16/4MX16 MCP PLASTIC PBF TFBGA 1.8V COMBO - Tape and Reel
PF38F3050M0Y0CEB TR 制造商:Micron Technology Inc 功能描述:IC FLASH 192M
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價(jià)

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*