參數(shù)資料
型號(hào)： PF38F3050L0YUQ3A
廠商： INTEL CORP
元件分類： 存儲(chǔ)器
英文描述： SPECIALTY MEMORY CIRCUIT, PBGA88
封裝： 8 X 10 MM, 1.20 MM HEIGHT, ROHS COMPLIANT, SCSP-88
文件頁(yè)數(shù)： 47/70頁(yè)
文件大?。?/td> 1193K
代理商： PF38F3050L0YUQ3A
Intel StrataFlash Wireless Memory (L18 SCSP)
August 2006
Datasheet
Order Number: 314476-001
51
768-Mbit LQ Family with Synchronous PSRAM
11.2.4
PSRAM Synchronous Set Control Register Write
In the full Synchronous mode the contents of the BCR and RCR can be set
synchronously. To initiate a synchronous Set Control Register:
CE#, WE#, ADV#, and CRE must be asserted; and
OE# must be deasserted;
Address is latched on the rising edge of the clock
The DQ signals are ignored by the PSRAM and therefore the WAIT signal should be
ignored. Address bits A19 and A18 specify the target register (RCR = 00b, BCR = 10b.)
The values of the remaining address bits are loaded into the selected register. The Set
Control Register command should only be issued when the PSRAM is in the idle state
(deselected).
Warning:
When operating the PSRAM as an ADMux I/O interface by connecting the lower sixteen
(16) addresses, A[15:0], to the data pins, ADV# must be de-asserted during any data
phase cycle.
11.3
PSRAM No Operation Command
The No Operation (NOP) command is used to perform a no operation to a selected
PSRAM (CE# = Low) Operations in progress are not affected. A NOP may be issued in
Asynchronous, Synchronous, or NOR-Flash mode. To initiate a NOP:
CE#, must be asserted;
WE#, ADV#, OE#, and CRE must be deasserted; and
CLK must be held in a static low state while in Asynchronous mode. CLK may toggle
during a NOP in Synchronous mode.
In Synchronous mode, ADV# deasserted hold time (tHD) must be observed.
Warning:
When operating the PSRAM as an ADMux I/O interface by connecting the lower sixteen
(16) addresses, A[15:0], to the data pins, ADV# must be de-asserted during any data
phase cycle.
11.4
PSRAM Deselect
The Deselect function prevents new commands from being executed by the PSRAM. A
deselected PSRAM places its I/O signals in a high impedance state. To place the device
in a deselected state:
CE# must be deasserted.
CLK must be held in a static low state while in Asynchronous mode. CLK may toggle
during a NOP in Synchronous mode.
11.5
PSRAM Deep Power Down
Deep Power Down (DPD) stops all refresh-related activities and the current
consumption of the device drops to a very low level. The contents of the Memory are
not preserved. After setting RCR4 = 1b, to place the device in the DPD state
CE# must be deasserted.
CLK must be held in a static low state to achieve minimum current consumption
levels.
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