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參數(shù)資料
| 型號(hào)： | PF38F3050L0YUQ3A |
| 廠商： | INTEL CORP |
| 元件分類： | 存儲(chǔ)器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PBGA88 |
| 封裝： | 8 X 10 MM, 1.20 MM HEIGHT, ROHS COMPLIANT, SCSP-88 |
| 文件頁數(shù)： | 53/70頁 |
| 文件大?。?/td> | 1193K |
| 代理商： | PF38F3050L0YUQ3A |
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Intel StrataFlash Wireless Memory (L18 SCSP)
August 2006
Datasheet
Order Number: 314476-001
57
768-Mbit LQ Family with Synchronous PSRAM
12.2.1.4
PSRAM WAIT Polarity BCR Bit
The WAIT polarity control bit allows the user to define the polarity of the WAIT output
signal. The WAIT output line is used during a variable latency synchronous read burst
to signal when the output data is invalid. Active low WAIT polarity means that when
WAIT is asserted low, output data is invalid. Similarly active high WAIT polarity means
that when WAIT is asserted high, output data is invalid.
12.2.1.5
PSRAM WAIT Configuration BCR Bit
The WAIT signal configuration control bit specifies whether the WAIT signal is asserted
at the time of the delay or whether it is asserted one clock cycle in advance of the
delay.
12.2.1.6
PSRAM Drive Strength BCR Bit
For adaptation to different system characteristics the output impedance can be
configured. Full drive strength is targeted for 25-30 Ohm systems, half drive strength is
targeted for 50 Ohm systems, and quarter drive strength is targeted for 100 Ohm
systems.
Table 21. Optional PSRAM BCR Latency Counter Settings in Fixed Latency
Latency
Counter
PSRAM
010
Code 2; Max 33 MHz
011
Code 3; Max 52 MHz
100
Code 4; Max 66 MHz
101
Code 5; Max 75 Mhz
110
Code 6; Max 104 MHz
Others
Reserved
Figure 31. Example of the Latency of First Valid Data in Synchronous Mode
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