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參數(shù)資料
| 型號： | pentium processor with MMX |
| 廠商： | Intel Corp. |
| 英文描述： | 32-bit processor with MMX technology(32位帶MMX技術(shù)處理器) |
| 中文描述： | 32位MMX技術(shù)（32位帶MMX公司的技術(shù)處理器處理器） |
| 文件頁數(shù)： | 8/51頁 |
| 文件大?。?/td> | 479K |
| 代理商： | PENTIUM PROCESSOR WITH MMX |
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PENTIUM PROCESSOR WITH MMX TECHNOLOGY
E
8
5/23/97 10:47 AM 24318502.DOC
The integration of the MMX pipeline with the integer
pipeline is very similar to that of the floating-point
pipeline. Under some circumstances, two MMX
instructions or one integer and one MMX instruction
can be paired and issued in one clock cycle to
increase throughput.
The enhanced pipeline is described in more detail in
the Pentium
Processor Family Developer’s Manual
(Order Number 241428).
1.2.5.
DEEPER WRITE BUFFERS
A pool of four write buffers is now shared between
the dual pipelines to improve memory write
performance.
1.3.
Mobile Pentium
Processor
with MMX Technology
Currently, Intel’s Mobile Pentium processor with
MMX technology family consists of three products.
Detailed information on Mobile Pentium processors
with MMX technology based on the enhanced CMOS
process technology is available in the datasheet
Mobile Pentium
Processor with MMX Technology
(Order Number 243292). Please reference the
datasheet for correct pinout, mechanical, thermal and
electrical specifications.
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