PENTIUM PROCESSOR WITH MMX TECHNOLOGY
E
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5/23/97 10:47 AM 24318502.DOC
NOTES:
1.
This value should be used for power supply design. It was determined using a worst case instruction mix and maximum
V
CC
. Power supply transient response and decoupling capacitors must be sufficient to handle the instantaneous current
changes occurring during transitions from Stop Clock to full Active modes.
Table 13. Power Dissipation Requirements for Thermal Design
(Measured at V
CC2
=2.8V and V
CC3
=3.3V.)
Parameter
Typical
(1)
Max
(2)
Unit
Notes
Active Power
7.9
(5)
7.3
(5)
6.1
(5)
17.0
(6)
15.7
(6)
13.1
(6)
Watts
Watts
Watts
233 MHz
200 MHz
166 MHz
Stop Grant / Auto Halt
Powerdown Power
2.61
2.41
2.05
Watts
Watts
Watts
233 MHz
200 MHz
(3)
166 MHz
(3)
(3)
Stop Clock Power
0.03
< 0.3
Watts
All frequencies
(4)
NOTES:
1.
This is the typical power dissipation in a system. This value is expected to be the average value that will be measured in a
system using a typical device at V
CC2
= 2.8V running typical applications. This value is highly dependent upon the specific
system configuration. Typical power specifications are not tested.
Systems must be designed to thermally dissipate the maximum active power dissipation. It is determined using worst case
instruction mix with V
CC2
= 2.8V and V
CC3
= 3.3 and also takes into account the thermal time constants of the package.
Stop Grant/Auto Halt Power Down Power Dissipation is determined by asserting the STPCLK# pin or executing the HALT
instruction.
Stop Clock Power Dissipation is determined by asserting the STPCLK# pin and then removing the external CLK input.
Active Power (typ) is the average power measured in a system using a typical device running typical applications under
normal operating conditions at nominal V
CC
and room temperature.
Active Power (max) is the maximum power dissipation under normal operating conditions at nominal V
CC2
, worst-case
temperature, while executing the worst case power instruction mix. Active power (max) is equivalent to Thermal Design
Power (max).
2.
3.
4.
5.
6.