參數(shù)資料
型號(hào)： pentium processor with MMX
廠商： Intel Corp.
英文描述： 32-bit processor with MMX technology(32位帶MMX技術(shù)處理器)
中文描述： 32位MMX技術(shù)（32位帶MMX公司的技術(shù)處理器處理器）
文件頁數(shù)： 17/51頁
文件大?。?/td> 479K
代理商： PENTIUM PROCESSOR WITH MMX
E
PENTIUM PROCESSOR WITH MMX TECHNOLOGY
17
5/23/97 10:47 AM 24318502.DOC
Table 2. Quick Pin Reference
(Cont’d)
Symbol
Type
Name and Function
D/P#
O
The
dual/primary
processor indication. The Primary processor drives this pin low
when it is driving the bus, otherwise it drives this pin high. D/P# is always driven.
D/P# can be sampled for the current cycle with ADS# (like a status pin). This pin
is defined only on the Primary processor. Dual processing is supported in a
system only if both processors are operating at identical core and bus
frequencies. Within these restrictions, two processors of different steppings may
operate together in a system.
D63-D0
I/O
These are the 64
data lines
for the processor. Lines D7-D0 define the least
significant byte of the data bus; lines D63-D56 define the most significant byte of
the data bus. When the CPU is driving the data lines, they are driven during the
T2, T12, or T2P clocks for that cycle. During reads, the CPU samples the data
bus when BRDY# is returned.
DP7-DP0
I/O
These are the
data parity
pins for the processor. There is one for each byte of the
data bus. They are driven by the Pentium processor with MMX technology with
even parity information on writes in the same clock as write data. Even parity
information must be driven back to the Pentium processor with MMX technology
on these pins in the same clock as the data to ensure that the correct parity check
status is indicated by the Pentium processor with MMX technology. DP7 applies
to D63-56, DP0 applies to D7-0.
[DPEN#]
PICD0
I/O
Dual processing enable
is an output of the Dual processor and an input of the
Primary processor. The Dual processor drives DPEN# low to the Primary
processor at RESET to indicate that the Primary processor should enable dual
processor mode. DPEN# may be sampled by the system at the falling edge of
RESET to determine if the dual-processor socket is occupied. DPEN# is
multiplexed with PICD0.
EADS#
I
This signal indicates that a valid
external address
has been driven onto the
Pentium processor with MMX technology address pins to be used for an inquire
cycle.
EWBE#
I
The
external write buffer empty
input, when inactive (high), indicates that a write
cycle is pending in the external system. When the Pentium processor with MMX
technology generates a write, and EWBE# is sampled inactive, the Pentium
processor with MMX technology will hold off all subsequent writes to all E- or M-
state lines in the data cache until all write cycles have completed, as indicated by
EWBE# being active.
FERR#
O
The
floating-point error
pin is driven active when an unmasked
floating-point
error occurs. FERR# is similar to the ERROR# pin on the Intel387 math
coprocessor. FERR# is included for compatibility with systems using DOS type
floating-point
error reporting. FERR# is never driven active by the Dual
processor.
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