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| 型號： | pentium processor with MMX |
| 廠商： | Intel Corp. |
| 英文描述： | 32-bit processor with MMX technology(32位帶MMX技術(shù)處理器) |
| 中文描述： | 32位MMX技術(shù)（32位帶MMX公司的技術(shù)處理器處理器） |
| 文件頁數(shù)： | 22/51頁 |
| 文件大小： | 479K |
| 代理商： | PENTIUM PROCESSOR WITH MMX |
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PENTIUM PROCESSOR WITH MMX TECHNOLOGY
E
22
5/23/97 10:47 AM 24318502.DOC
Table 2. Quick Pin Reference
(Cont’d)
Symbol
Type
Name and Function
RESET
I
RESET
forces the Pentium processor with MMX technology to begin execution at
a known state. All the Pentium processor with MMX technology internal caches
will be invalidated upon the RESET. Modified lines in the data cache are not
written back. FLUSH# and INIT are sampled when RESET transitions from high to
low to determine if tristate test mode or checker mode will be entered, or if Built-In
Self-Test (BIST) will be run.
SCYC
O
The
split cycle
output is asserted during misaligned LOCKed transfers to indicate
that more than two cycles will be locked together. This signal is defined for locked
cycles only. It is undefined for cycles which are not locked.
SMI#
I
The
system management interrupt
causes a system management interrupt
request to be latched internally. When the latched SMI# is recognized on an
instruction boundary, the processor enters System Management Mode.
SMIACT#
O
An active
system management interrupt active
output indicates that the
processor is operating in System Management Mode.
STPCLK#
I
Assertion of the
stop clock
input signifies a request to stop the internal clock of
the Pentium processor with MMX technology, thereby causing the core to
consume less power. When the CPU recognizes STPCLK#, the processor will
stop execution on the next instruction boundary, unless superseded by a higher
priority interrupt, and generate a stop grant acknowledge cycle. When STPCLK#
is asserted, the Pentium processor with MMX technology will still respond to
interprocessor and external snoop requests.
TCK
I
The
testability clock
input provides the clocking function for the Pentium
processor with MMX technology boundary scan in accordance with the IEEE
Boundary Scan interface (Standard 1149.1). It is used to clock state information
and data into and out of the Pentium processor with MMX technology during
boundary scan.
TDI
I
The
test data input
is a serial input for the test logic. TAP instructions and data
are shifted into the Pentium processor with MMX technology on the TDI pin on the
rising edge of TCK when the TAP controller is in an appropriate state.
TDO
O
The
test data output
is a serial output of the test logic. TAP instructions and data
are shifted out of the Pentium processor with MMX technology on the TDO pin on
TCK’s falling edge when the TAP controller is in an appropriate state.
TMS
I
The value of the
test mode select
input signal sampled at the rising edge of TCK
controls the sequence of TAP controller state changes.
TRST#
I
When asserted, the
test reset
input allows the TAP controller to be
asynchronously initialized.
V
CC2
I
The Pentium processor with MMX technology has 25 2.8V
power
inputs.
V
CC3
I
The Pentium processor with MMX technology has 28 3.3V
power
inputs.
V
CC2
DET#
O
V
CC2
detect
is used in flexible motherboard implementations to configure the
voltage output set-point appropriately for the V
CC2
inputs of the processor.
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