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| 型號： | pentium processor with MMX |
| 廠商： | Intel Corp. |
| 英文描述： | 32-bit processor with MMX technology(32位帶MMX技術(shù)處理器) |
| 中文描述： | 32位MMX技術(shù)（32位帶MMX公司的技術(shù)處理器處理器） |
| 文件頁數(shù)： | 15/51頁 |
| 文件大小： | 479K |
| 代理商： | PENTIUM PROCESSOR WITH MMX |
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E
PENTIUM PROCESSOR WITH MMX TECHNOLOGY
15
5/23/97 10:47 AM 24318502.DOC
Table 2. Quick Pin Reference
(Cont’d)
Symbol
Type
Name and Function
BE7#
–BE4#
BE3#–BE0#
O
I/O
The
byte enable
pins are used to determine which bytes must be written to
external memory or which bytes were requested by the CPU for the current cycle.
The byte enables are driven in the same clock as the address lines (A31-3).
Additionally, the lower 4-byte enables (BE3#-BE0#) are used on the Pentium
processor with MMX technology as APIC ID inputs and are sampled at RESET.
In dual processing mode, BE4# is used as an input during Flush cycles.
BF[1:0]
I
The
bus frequency
pins determine the bus-to-core frequency ratio. BF[1:0] are
sampled at RESET, and cannot be changed until another non-warm (1 ms)
assertion of RESET. Additionally, BF[1:0] must not change values while RESET is
active. See Table 3 for Bus Frequency Selections.
BOFF#
I
The
backoff
input is used to abort all outstanding bus cycles that have not yet
completed. In response to BOFF#, the Pentium processor with MMX technology
will float all pins normally floated during bus hold in the next clock. The processor
remains in bus hold until BOFF# is negated, at which time the Pentium processor
with MMX technology restarts the aborted bus cycle(s) in their entirety.
BP[3:2]
PM/BP[1:0]
O
The
breakpoint
pins (BP3-0) correspond to the debug registers, DR3-DR0.
These pins externally indicate a breakpoint match when the debug registers are
programmed to test for breakpoint matches.
BP1 and BP0 are multiplexed with the
performance monitoring
pins (PM1 and
PM0). The PB1 and PB0 bits in the Debug Mode Control Register determine if the
pins are configured as breakpoint or performance monitoring pins. The pins come
out of RESET configured for performance monitoring.
BRDY#
I
The
burst ready
input indicates that the external system has presented valid data
on the data pins in response to a read or that the external system has accepted
the Pentium processor with MMX technology data in response to a write request.
This signal is sampled in the T2, T12 and T2P bus states.
BRDYC#
I
The
burst ready (copy)
is functionally identical to BRDY#.
BREQ
O
The
bus request
output indicates to the external system that the Pentium
processor with MMX technology has internally generated a bus request. This
signal is always driven whether or not the Pentium processor with MMX
technology is driving its bus.
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