參數(shù)資料
型號(hào)： pentium processor with MMX
廠商： Intel Corp.
英文描述： 32-bit processor with MMX technology(32位帶MMX技術(shù)處理器)
中文描述： 32位MMX技術(shù)（32位帶MMX公司的技術(shù)處理器處理器）
文件頁(yè)數(shù)： 39/51頁(yè)
文件大?。?/td> 479K
代理商： PENTIUM PROCESSOR WITH MMX
E
PENTIUM PROCESSOR WITH MMX TECHNOLOGY
39
5/23/97 10:47 AM 24318502.DOC
Table 16. Pentium
Processor with MMX Technology Dual Processor Mode
AC Specifications for 66-MHz Bus Operation
(See Table 10 for V
CC
and T
CASE
assumptions.)
Symbol
Parameter
Min
Max
Unit
Figure
Notes
t
80a
PBREQ#, PBGNT#, PHIT#
Flight Time
0.0
2.0
ns
5
(11, 24)
t
80b
PHITM# Flight Time
0.0
1.8
ns
5
(11, 24)
t
83a
A5-A31 Setup Time
3.7
ns
7
(18)
t
83b
D/C#, W/R#, CACHE#,
LOCK#, SCYC Setup Time
4.0
ns
7
(18, 21)
t
83c
ADS#, M/IO# Setup Time
5.8
ns
7
(18, 21)
t
83d
HIT#, HITM# Setup Time
6.0
ns
7
(18, 21)
t
83e
HLDA Setup Time
6.0
ns
7
(18, 21)
t
84a
CACHE#, HIT# Hold Time
1.0
ns
7
(18, 21)
t
84b
ADS#, D/C#, W/R#, M/IO#,
A5-A31, HLDA, SCYC Hold
Time
0.8
ns
7
(18, 21)
t
84c
LOCK# Hold Time
0.9
ns
7
(18, 21)
t
84d
HITM# Hold Time
0.7
ns
7
(18, 21)
t
85
DPEN# Valid Time
10.0
CLK
(18, 19, 23)
t
86
DPEN# Hold Time
2.0
CLK
(18, 20, 23)
t
87
APIC ID (BE0#-BE3#) Setup
Time
2.0
CLK
8
To falling Edge of
RESET
(23)
t
88
APIC ID (BE0#-BE3#) Hold
Time
2.0
CLK
8
From Falling Edge of
RESET
(23)
t
89
D/P# Valid Delay
1.0
8.0
ns
5
Primary Processor Only
NOTES:
Notes 2, 6 and 14 are general and apply to all standard TTL signals used with the Pentium
processor family.
Each valid delay is specified for a 0 pF load. The system designer should use I/O buffer models to account for signal flight time
delays.
1.
Not 100% tested. Guaranteed by design/characterization.
2.
TTL input test waveforms are assumed to be 0 to 3V transitions with 1 V/ns rise and fall times.
3.
Non-test outputs and inputs are the normal output or input signals (besides TCK, TRST#, TDI, TDO and TMS). These
timings correspond to the response of these signals due to boundary scan operations.
4.
APCHK#, FERR#, HLDA, IERR#, LOCK# and PCHK# are glitch-free outputs. Glitch-free signals monotonically transition
without false transitions (i.e., glitches).
5.
0.8V/ns ( CLK input rise/fall time
≤
8V/ns.
6.
0.3V/ns ( input rise/fall time
≤
5V/ns.
7.
Referenced to TCK rising edge.
8.
Referenced to TCK falling edge.
9.
1 ns can be added to the maximum TCK rise and fall times for every 10 MHz of frequency below 33 MHz.
10. During debugging, do not use the boundary scan timings (t
55
to t
58
).
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