參數(shù)資料
型號： pentium processor with MMX
廠商： Intel Corp.
英文描述： 32-bit processor with MMX technology(32位帶MMX技術(shù)處理器)
中文描述： 32位MMX技術(shù)（32位帶MMX公司的技術(shù)處理器處理器）
文件頁數(shù)： 14/51頁
文件大小： 479K
代理商： PENTIUM PROCESSOR WITH MMX
PENTIUM PROCESSOR WITH MMX TECHNOLOGY
E
14
5/23/97 10:47 AM 24318502.DOC
The # symbol at the end of a signal name indicates
that the active, or asserted state occurs when the
signal is at a low voltage. When a # symbol is not
present after the signal name, the signal is active, or
asserted at the high voltage level. Square brackets
around a signal name indicate that the signal is
defined only at RESET.
The following pins become I/O pins when two
Pentium processors with MMX technology are
operating in a dual processing environment:
ADS#, CACHE#, HIT#, HITM#, HLDA#, LOCK#,
M/IO#, D/C#, W/R#, SCYC, BE#4
Table 2. Quick Pin Reference
Symbol
Type
Name and Function
A20M#
I
When the
address bit 20 mask
pin is asserted, the Pentium
processor with
MMX technology emulates the address wraparound at 1 Mbyte which occurs on
the 8086 by masking physical address bit 20 (A20) before performing a lookup to
the internal caches or driving a memory cycle on the bus. The effect of A20M# is
undefined in protected mode. A20M# must be asserted only when the processor
is in real mode.
A20M# is internally masked by the Pentium processor with MMX technology when
configured as a Dual processor.
A31-A3
I/O
As outputs, the
address
lines of the processor along with the byte enables define
the physical area of memory or I/O accessed. The external system drives the
inquire address to the processor on A31-A5.
ADS#
O
The
address strobe
indicates that a new valid bus cycle is currently being driven
by the Pentium processor with MMX technology.
ADSC#
O
The
address strobe (copy)
is functionally identical to ADS#.
AHOLD
I
In response to the assertion of
address hold
, the Pentium processor with MMX
technology will stop driving the address lines (A31-A3) and AP in the next clock.
The rest of the bus will remain active so data can be returned or driven for
previously issued bus cycles.
AP
I/O
Address parity
is driven by the Pentium processor with MMX technology with
even parity information on all Pentium processor with MMX technology generated
cycles in the same clock that the address is driven. Even parity must be driven
back to the Pentium processor with MMX technology during inquire cycles on this
pin in the same clock as EADS# to ensure that correct parity check status is
indicated by the Pentium processor with MMX technology.
APCHK#
O
The
address parity check
status pin is asserted two clocks after EADS# is
sampled active if the Pentium processor with MMX technology has detected a
parity error on the address bus during inquire cycles. APCHK# will remain active
for one clock each time a parity error is detected (including during dual processing
private snooping).
[APICEN]
PICD1
I
Advanced Programmable Interrupt Controller Enable
enables or disables the
on-chip APIC interrupt controller. If sampled high at the falling edge of RESET, the
APIC is enabled. APICEN shares a pin with the PICD1 signal.
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