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| 型號(hào)： | pentium processor with MMX |
| 廠商： | Intel Corp. |
| 英文描述： | 32-bit processor with MMX technology(32位帶MMX技術(shù)處理器) |
| 中文描述： | 32位MMX技術(shù)（32位帶MMX公司的技術(shù)處理器處理器） |
| 文件頁數(shù)： | 34/51頁 |
| 文件大?。?/td> | 479K |
| 代理商： | PENTIUM PROCESSOR WITH MMX |
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PENTIUM PROCESSOR WITH MMX TECHNOLOGY
E
34
5/23/97 10:47 AM 24318502.DOC
3.4.
AC Specifications
The AC specifications consist of output delays, input
setup requirements and input hold requirements. All
AC specifications (with the exception of those for the
TAP signals and APIC signals) are relative to the
rising edge of the CLK input.
All timings are referenced to 1.5 volts for both "0" and
"1" logic levels unless otherwise specified. Within the
sampling window, a synchronous input must be
stable for correct Pentium processor with MMX
technology operation.
Each valid delay is specified for a 0 pF load. The
system designer should use I/O buffer modeling to
account for signal flight time delays.
Each Pentium processor with MMX technology
specified to operate within a single bus-to-core ratio
and a specific minimum to maximum bus frequency
range (corresponding to a minimum to maximum
core frequency range). Operation in other bus-to-
core ratios or outside the specified operating
frequency range is not supported. For example, the
166 MHz Pentium processor with MMX technology
does not operate beyond the 66 MHz bus frequency
and only supports the 2/5 bus-to-core ratio; it does
not support the 1/3, 1/2, or 2/3 bus-to-core ratios.
Table 3
clarifies
and
specifications.
summarizes
these
Table 15. Pentium
Processor with MMX Technology AC Specifications for
66-MHz Bus Operation
(See Table 10 for V
CC
and T
CASE
specifications, C
L
= 0 pF.)
Symbol
Parameter
Min
Max
Unit
Figure
Notes
Frequency
33.33
66.6
MHz
4
t
1a
CLK Period
15.0
30.0
ns
4
t
1b
CLK Period Stability
±250
ps
Adjacent Clocks
(1, 25)
t
2
CLK High Time
4.0
ns
4
2V
(1)
t
3
CLK Low Time
4.0
ns
4
0.8V
(1)
t
4
CLK Fall Time
0.15
1.5
ns
4
(2.0V–0.8V)
(1, 5)
t
5
CLK Rise Time
0.15
1.5
ns
4
(0.8V–2.0V)
(1, 5)
t
6a
PWT, PCD, CACHE# Valid
Delay
1.0
7.0
ns
5
t
6b
AP Valid Delay
1.0
8.5
ns
5
t
6c
BE0-7#, LOCK# Valid Delay
0.9
7.0
ns
5
(4)
t
6d
ADS# Valid Delay
0.8
6.0
ns
5
t
6e
ADSC#, D/C#, W/R#, SCYC,
Valid Delay
0.8
7.0
ns
5
t
6f
M/IO# Valid Delay
0.8
5.9
ns
5
t
6g
A3–A16 Valid Delay
0.5
6.6
ns
5
t
6h
A17–A31 Valid Delay
0.6
6.6
ns
5
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