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| 型號： | pentium processor with MMX |
| 廠商： | Intel Corp. |
| 英文描述： | 32-bit processor with MMX technology(32位帶MMX技術(shù)處理器) |
| 中文描述： | 32位MMX技術(shù)（32位帶MMX公司的技術(shù)處理器處理器） |
| 文件頁數(shù)： | 18/51頁 |
| 文件大?。?/td> | 479K |
| 代理商： | PENTIUM PROCESSOR WITH MMX |
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PENTIUM PROCESSOR WITH MMX TECHNOLOGY
E
18
5/23/97 10:47 AM 24318502.DOC
Table 2. Quick Pin Reference
(Cont’d)
Symbol
Type
Name and Function
FLUSH#
I
When asserted, the
cache flush
input forces the Pentium processor with MMX
technology to write back all modified lines in the data cache and invalidate its
internal caches. A Flush Acknowledge special cycle will be generated by the
Pentium processor with MMX technology indicating completion of the write back
and invalidation.
If FLUSH# is sampled low when RESET transitions from high to low, tristate test
mode is entered.
If two Pentium processors with MMX technology are operating in dual processing
mode and FLUSH# is asserted, the Dual processor will perform a flush first
(without a flush acknowledge cycle), then the Primary processor will perform a
flush followed by a flush acknowledge cycle.
NOTE:
If the FLUSH# signal is asserted in dual processing mode, it must be deasserted
at least one clock prior to BRDY# of the FLUSH Acknowledge cycle to avoid DP
arbitration problems.
FRCMC#
I
Functional Redundancy Checking is not supported on the Pentium processor with
MMX technology. The FRCMC# pin is not defined for the Pentium processor with
MMX technology. This pin should be left as a
“NC” or tied to V
CC3
via an external
pull-up resistor.
HIT#
O
The
hit
indication is driven to reflect the outcome of an inquire cycle. If an inquire
cycle hits a valid line in either the Pentium processor with MMX technology data or
instruction cache, this pin is asserted two clocks after EADS# is sampled
asserted. If the inquire cycle misses the Pentium processor with MMX technology
cache, this pin is negated two clocks after EADS#. This pin changes its value only
as a result of an inquire cycle and retains its value between the cycles.
HITM#
O
The
hit to a modified line
output is driven to reflect the outcome of an inquire
cycle. It is asserted after inquire cycles which resulted in a hit to a modified line in
the data cache. It is used to inhibit another bus master from accessing the data
until the line is completely written back.
HLDA
O
The
bus hold acknowledge
pin goes active in response to a hold request driven
to the processor on the HOLD pin. It indicates that the Pentium processor with
MMX technology has floated most of the output pins and relinquished the bus to
another local bus master. When leaving bus hold, HLDA will be driven inactive
and the Pentium processor with MMX technology will resume driving the bus. If
the Pentium processor with MMX technology has a bus cycle pending, it will be
driven one clock cycle after HLDA is de-asserted.
HOLD
I
In response to the
bus hold request
, the Pentium processor with MMX
technology will float most of its output and input/output pins and assert HLDA after
completing all outstanding bus cycles. The Pentium processor with MMX
technology will maintain its bus in this state until HOLD is de-asserted. HOLD is
not recognized during LOCK cycles. The Pentium processor with MMX
technology will recognize HOLD during reset.
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