參數(shù)資料
型號(hào)： pentium II cpu with mobile
廠商： Intel Corp.
英文描述： pentium II processor With On-die Cache Mobile Module Connector 2 (MMC-2)(帶緩存和連接器2的奔II處理器)
中文描述： 奔騰II處理器芯片上緩存手機(jī)模塊連接器2（絲裂霉素2）（帶緩存和連接器2的奔二處理器）
文件頁(yè)數(shù)： 5/48頁(yè)
文件大小： 537K
代理商： PENTIUM II CPU WITH MOBILE
Intel
a
Pentium
a
II Processor With On-Die Cache Mobile Module MMC-2
5
1.0
INTRODUCTION
This document provides the technical information for
integrating the Pentium II processor with on-die cache
mobile module Connector 2 (MMC-2) into the latest
notebook systems for today’s notebook market.
Building around this design gives the system manufacturer
these advantages:
Avoids complexities associated with designing high-
speed processor core logic boards.
Provides an upgrade path from previous Intel
Mobile
Modules using a standard interface.
1.1
Revision History
Date
Revision
Updates
2/ 1999
1.0
Initial release
Updates include:
Addition of the 400-MHz
processor speed
POS/STR measurement
corrections
ESD specification clarification
VR_ON and VR_PWRGD
specification correction
L2 cache specification correction
Power sequence clarification
Revised Table 24
5/ 1999
2.0
2/ 2000
3.0
2.0
ARCHITECTURE OVERVIEW
A highly integrated assembly, the Pentium II processor with
on-die cache mobile module MMC-2 contains the mobile
Pentium II processor with on-die cache core and its
immediate system-level support. The Pentium II processor
with on-die cache mobile module MMC-2 offers core speeds
of 400 megahertz, 366 megahertz, 333 megahertz, 300
megahertz, and 266 megahertz. All processor speeds have
a 66-megahertz processor system bus speed (PSB).
The PIIX4E/M PCI/ISA Bridge is one of two large-scale
integrated devices of the Intel 440BX AGPset. A notebook’s
system electronics must include a PIIX4E/M device to
connect to the Pentium II processor with on-die cache
mobile module MMC-2. The PIIX4E/M provides extensive
power management capabilities and supports the Intel
82433BX Host Bridge, the second integrated device. Key
features of the 82433BX Host Bridge include the DRAM
controller, which supports EDO at 3.3 volts with a burst read
at 7-2-2-2 (60 nanoseconds) or SDRAM at 3.3 volts with a
burst read at 8-1-1-1 (66 megahertz, CL=2). The 82433BX
Host Bridge also provides a PCI CLKRUN# signal to request
PIIX4E/M to regulate the PCI clock on the PCI bus. The
82433BX clock enables Self Refresh mode of EDO or
SDRAM during Suspend mode and is compatible with
SMRAM (C_SMRAM) and Extended SMRAM (E_SMRAM)
modes of power management. E_SMRAM mode supports
write-back cacheable SMRAM up to 1 megabyte.
A thermal transfer plate (TTP) on the 82433BX Host Bridge
and the CPU provides heat dissipation and a thermal attach
point for the system manufacturer’s thermal solution.
An on-board voltage regulator converts the system DC
voltage to the processor’s core and I/O voltage. Isolating the
processor voltage requirements allows the system
manufacturer to incorporate different processor variants into
a single notebook system.
Supporting input voltages from 5 volts to 21 volts, the
processor core voltage regulation enables an above 80
percent peak efficiency and decouples processor voltage
requirements from the system.
The Pentium II processor with on-die cache mobile module
MMC-2 also incorporates Active Thermal Feedback (ATF)
sensing, compliant to the
ACPI Specification Rev 1.0
. A
system management bus (SMBus) supports the internal and
external temperature sensing with programmable trip points.
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