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| 型號： | pentium II cpu with mobile |
| 廠商： | Intel Corp. |
| 英文描述： | pentium II processor With On-die Cache Mobile Module Connector 2 (MMC-2)(帶緩存和連接器2的奔II處理器) |
| 中文描述： | 奔騰II處理器芯片上緩存手機模塊連接器2（絲裂霉素2）（帶緩存和連接器2的奔二處理器） |
| 文件頁數： | 11/48頁 |
| 文件大?。?/td> | 537K |
| 代理商： | PENTIUM II CPU WITH MOBILE |
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Intel
a
Pentium
a
II Processor With On-Die Cache Mobile Module MMC-2
11
3.1.4
PCI (58 Signals)
Table 4 lists the PCI interface signals.
Table 4. PCI Signal Descriptions
Name
Type
Voltage
Description
AD[31:0]
I/O
PCI
I/O
PCI
I/O
PCI
I/O
PCI
I/O
PCI
I/O
PCI
I/O
PCI
I/O
PCI
V_3
Address/Data:
The standard PCI address and data lines. The address is driven with
FRAME# assertion and data is driven or received in the following clocks.
C/BE[3:0]#
V_3
Command/Byte Enable:
The command is driven with FRAME# assertion and byte
enables corresponding to supplied or requested data are driven on the following clocks.
FRAME#
V_3
Frame:
Assertion indicates the address phase of a PCI transfer. Negation indicates that
the cycle initiator desires one more data transfer.
DEVSEL#
V_3
Device Select:
the 82433BX Host Bridge drives this signal when a PCI initiator is
attempting to access DRAM.
DEVSEL# is asserted at medium decode time.
IRDY#
V_3
Initiator Ready:
Asserted when the initiator is ready for data transfer.
TRDY#
V_3
Target Ready:
Asserted when the target is ready for a data transfer.
STOP#
V_3
Stop:
Asserted by the target to request the master to stop the current transaction.
PLOCK#
V_3
Lock:
Indicates an exclusive bus operation and may require multiple transactions to
complete. When LOCK# is asserted, nonexclusive transactions may proceed. The
82433BX supports lock for CPU initiated cycles only. PCI initiated locked cycles are not
supported.
REQ[4:0]#
I
PCI
O
PCI
I
PCI
V_3
PCI Request:
PCI master requests for PCI.
GNT[4:0]#
V_3
PCI Grant:
Permission is given to the master to use PCI.
PHOLD#
V_3
PCI Hold:
This signal comes from the expansion bridge; it is the bridge request for PCI.
The 82433BX Host Bridge will drain the DRAM write buffers, drain the processor-to-PCI
posting buffers, and acquire the host bus before granting the request via PHLDA#. This
ensures that GAT timing is met for ISA masters.
The PHOLD# protocol has been
modified to include support for passive release.
PHLDA#
O
PCI
V_3
PCI Hold Acknowledge:
This signal is driven by the 82433BX Host Bridge to grant PCI
to the expansion bridge.
The PHLDA# protocol has been modified to include support for
passive release.
PAR
I/O
PCI
I/O
PCI
I/O D
PCI
V_3
Parity:
A single parity bit is provided over AD[31:0] and C/BE[3:0]#.
SERR#
V_3
System Error:
The 82433BX asserts this signal to indicate an error condition. Refer to
the
Intel
a
440BX AGPset Datasheet
for further information.
CLKRUN#
V_3
Clock Run:
An open-drain output and input.
The 82433BX Host Bridge requests the
central resource (PIIX4E/M) to start or maintain the PCI clock by asserting CLKRUN#.
The 82433BX Host Bridge tri-states CLKRUN# upon deassertion of Reset (since CLK is
running upon deassertion of Reset).
PCI_RST#
I
CMOS
V_3
Reset:
When asserted, this signal asynchronously resets the 82433BX Host Bridge.
The
PCI signals also tri-state, compliant with
PCI Rev 2.1 Specifications
.
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